Research On Soft Error Estimation Of Combinational Circuits Induced By Single Event

With the progress of integrated circuit technology,the size of devices and the key charges decrease continuously,which makes the integrated circuits in electronic devices working in various radiation environments vulnerable to radiation interference,resulting in electronic device failure.Research shows that soft errors caused by high-energy particles in space environment have become the main mode affecting IC failure.Especially in the era of deep sub-meter and nanometer,the soft error in combinational circuits increase exponentially.The incident of high-energy particles may simultaneously affect two or more physically connected nodes in combinational circuits,resulting in single event multiple transients(SEMT),combinational circuits caused by single event transients(SET)and SEMT.Soft error become more and more important.At present,the method of using SPICE to evaluate SET faults has high accuracy,but because of the long simulation time,it is only suitable for the analysis of small scale and single structure single channel.Compared with SPICE simulation,the hardware-based fault simulation evaluation method has the characteristics of fast speed,and is suitable for large-scale circuits for soft error assessment and analysis.At present,only two transient errors are considered in the simulation evaluation of SEMT.However,previous studies have shown that three or more transient errors can not be ignored.On the basis of summarizing the generation mechanism and propagation characteristics of SET and SEMT in combinational circuits,the soft error evaluation technology of combinational circuits is deeply studied,and a soft error evaluation system based on analog SET and SEMT of FPGA is designed.For the basic combinational logic units in the standard cell library,the transient current source is added to the circuit simulation tool HSPICE based on transistor level to predict the transient pulse width.The two-dimensional transient pulse width on the basic combinational logic units caused by single particle under different deposition charge energies and different cell loads is given.The lookup table lays a foundation for the construction of hardware simulation and evaluation system based on FPGA.Considering the propagation characteristics of transient pulse in the circuit and the introduction of error transient pulse,a delay shielding model is established by using quantization delay method to simulate the three shielding effects and pulse broadening effects in the circuit,and the pulse injection of SET is realized by means of flip-flop scan chain.On the basis of SET injection model,according to the fault location characteristics of SEMT,a hardware injection model suitable for SEMT is designed.Considering the randomness of particle incidence in real environment,the SET and SEMT hardware simulation and evaluation system is built.Taking the reference circuit as the object,the simulation evaluation system based on FPGA is validated.The test vectors are generated randomly and the simulation of SET and SEMT of the reference circuit is completed.The rationality of the simulation method is verified by comparing with other methods.The soft error evaluation system based on the analog SET of FPGA designed in this paper predicts the pulse width of the basic unit of each function in the library file.It is suitable for the soft error evaluation of the synthetically optimized circuit,and it is easy to get the sensitive information of each node.It can provide help for the selective reinforcement of the circuit.The software error evaluation system based on analog SEMT of FPGA is designed,which considers two or more transient soft errors caused by a single particle,and can also get the sensitivity information of each node,which is helpful for the selective reinforcement of circuits.Moreover,the whole simulation and analysis process is faster because of the hardware based on FPGA.