Research On Soft Error Rate Considering Single Event Multiple Transient

With the development of semiconductor technology stepping into the deep-submicron era,soft error induced by single event effect has emerged as an important challenge of reliability for integrated circuit systems on spacecraft and aircraft,as well as device used in commercial and military systems on the ground.With the shrinking of the feature size,soft error rate(SER)caused by single event transients(SET)in logic circuit leads to an increasingly higher proportion of the SER per chip.Studies have shown that single event multiple transients(SEMT)may account for 40% of all SET due to the increase of charge sharing effect.Therefore,the impact of SEMT on the SER must be taken into account.To estimate the SER of circuits effectively in the early stage of circuit design,based on the existing soft error research,we proposed an algorithm to calculate SER of logic circuit,which takes SET,SEMT and a comprehensive consideration of the three masking effects during propagation into account.In this thesis,we modeled the generation,propagation and capture stage of SET pulse.Based on the model of SET generation probability,we converted the generation probability of a given environment into a function of gate's critical charge.The double exponential current source model was performed to simulate the generated current pulse,and the SPICE simulation was used to obtain the critical charge of each gate in the netlist.Based on the calculation of the generation probability,a SER calculation model that combined the consideration of three masking effects of logical,electrical and latch window masking in logic circuits was established.On the basis of sensitized paths obtained by analyzing logic masking,electrical masking attenuation and latch window masking probability were calculated for the transient pulses generated by each gate.In order to consider the probability effect of SEMT in logic circuit,we proposed a SEMT analysis model.We obtained the circuit topology by the netlist from the early stage of circuit design.Then we exact the adjacent fault pairs that may generate SEMT from circuit topology.We use the proposed analysis model to convert SEMT pulse into SET pulse equivalently to reduce the complexity for analyzing multiple transient.We implemented the proposed SER calculation algorithm that oriented for circuit's VerilogHDL design files.The results of the circuit's total SER and the contributions of each gate and memory cells to overall SER were obtained.The ranking of soft error sensitivity of each cell could provide a reference for selectively hardening at the circuit design stage.We used the proposed algorithm to calculate SER of the ISCAS'85 benchmark circuit under the 130 nm process.Then we compared the calculation results with literature to verify the effectiveness and accuracy of our proposed algorithm.We also designed a large-scale circuit Open MIPS processor and calculated its SER,which could further illustrate that our proposed algorithm is suitable for the calculation of SER of large-scale circuits,and the speed of our proposed method is much faster than the fault injection method.Finally,we studied the trend of SER of logic circuit changing with the operating frequency.We drew a conclusion that the SER of logic circuit increases with the operating frequency.In addition,we studied the trend of SER in combinational and sequential circuits changing with circuit scale.And we obtained that when the flux is fixed,the SER results of the same type of circuit increase approximately linearly with the circuit scale.This result could provide an idea for equivalent miniaturization analysis of large-scale circuits of the same type,which had certain reference significance.