Research On Single-event Induced Soft Errors In Nano CMOS Combinational Circuits

With the rapid development of China’s aerospace science and technology, the research on the radiation-hardened advanced integrated circuits(ICs) has become the main concern in industry and academia. With the technology scaling and clock frequency increasing, the soft error rate(SER) in the combinational circuits is dominating the total radiation-induced soft errors. This paper studies the SER analysis, measurement and hardening techniques for the combinational circuits in nanometer technology. The main works and contributions of this dissertation are as follows:(1) A timing-mixed SET pulse propagation algorithm is proposed to deal with the problem of re-convergence in combinational circuits. The simulation data of the impact of the pulse quenching effect on the SER of large combinational circuits is got. For the combinational circuit based on the standard cell, the pulse quenching effect is related to several factors, such as the distance between the standard cells, the logic state, and ions incident location. By modeling the relationship between the ions incident location and the the pulse quenching effect, the SER analysis approach considering the pulse quenching effect is designed. Simulation results show that the impact of the pulse quenching effect on the SER is closely related to the layout placement. For different benchmark circuits, the SER considering the pulse quenching effect can be reduced by 4-16%. When considering an optimized layout placement, the SER can be further reduced.(2) The MSET is evaluated from the point of sensitive area. The study shows that the vulnerability of MSET sensitive area is an order lower than the one of single SET sensitive area. A simple sensitive area model and calculation approach for the MSET is proposed. And based on the node probability approach, the generation and propagation of MSET are analyzed. Simulation results present that although the probability of the MSET propagating to the outputs is larger than the one the single SET propagating to the outputs, the generation of the MSET is far lower than the one of single SET.(3) The concept of effective sensitive area and effective SET pulse width is proposed to calculate the SER of large combinational circuits. The study presents that the SER analysis approach treating the drain area as the sensitive area will largely underestimate the SER. Grid-based approach is designed to re-define the sensitive area of logic cells. And the heavy-ion experiements are conducted to validate the concept. Experiment and simulation results present that the effective sensitive area is more close to the real case. The SER analysis method treating the drain area as the sensitive area will largely underestimate the SER, which will bring optimistic conclusion.(4) Location-based SER analysis technique is designed. The charge sharing effect, the pulse quenching effect, multiple SETs and angle can be considered in this technique. Simulation and experiment resuls show that this SER analysis technique can fairly reflect the real SER. The standard cells in the library are first characterized based on the grid-based approaches. By doing so, the relationship between the ion strike location and SET pulse width can be reflected. And then the SER analysis technique considering the ions strike location is proposed. This technique can consider the key factors affecting the SER in nanometer technology. Heavy-ion experiment results indicate that this platform can fairly reflect the SER. Also, the detailed circuit response can be captured.(5) Based on commercial 65 nm bulk technology, three novel test structures are designed to measure the SER of combinational circuits. And the heavy-ion experiment data on the SER pulse width distribution in the large combinational circuits are obtained. Based on the symmetrical idea, three novel test structures are designed to measure the SER of large combinational circuits. These test structures include the dynamic test structures based on inverter chain, the PMOS and NMOS charge sharing test structures, and the SER test structure of large combinational circuits. The heavy-ion experiment is conducted to obtain the SER of large combinational circuits. This is a significant progress for the SER measurement.(6) A multi-layer hardening approach is designed and implemented to harden the large combinational circuits. Simulation results present that this technique can reduce the SER by 66.8% with about 22.8% area overhead. Based on the previous research work, this paper presents a multi-layer hardening approach. A uniform framework is implemented to integrate these hardening techniques for different layers into the current EDA software. Simulation results show that this hardening approach can gain better performance. The multi-layer technique can be configured according to the requirement.