The Research On Soft Error Rate Estimation For Nanometer Digital Integrated Circuit

With continuous technology down-scaling, CMOS technology has stepped into nanometer era. As the integrated circuit has been widely used in production and daily life, the decreasing of device size, power supply voltage and critical charge have result into that the reliability of integrated circuit caused by space radiation meet huge challenge. In the nanoscale, the chip size grows Exponential. The transistor become more sensitive for neutron and high-energy particle radiation, so the probability of chips influenced by soft error is also greatly increased. In this case, a high energy particle can affect two or more adjacent nodes in a circuit resulting in Multiple Event Transients (METs) in the combinational. As the circuit failure caused by SEMT becomes more and more important, the soft error has become one of the important reasons for the failure of IC.To accurately compute the soft error probability of different digital circuits, a soft error rate estimation method considering SEMT is proposed. This method basing on the probability calculation method evaluates the soft error rate of nanometer integrated circuits. Thus the proposed method is valuable to fault tolerance design of ICs for selective hardening and also can reduce the cost of IC design. The main research contents and innovations are as follows.To begin with, we introduced the concepts of soft errors and the relevant factors of circuit reliability, as well as research achievements. The mechanism of soft errors, propagation characteristics and evaluation method are analyzed in detail. The digital circuit soft error rate evaluation methods considering SET or SEMT is emphatically described, and the advantages and disadvantages of each method are analyzed. When the integrated circuits are in the gate level, the corresponding soft error characterization and propagation characteristics are also introduced in depth. Based on the existing soft error rate estimation technique, an accurate model for evaluating the circuit soft error rate of SEMT is realized.What’s more, as to incomplete input-vector space and slower SER estimation speed for input vector based methods, a probability based SER analysis model for nanoscale ICs is realized. The pulse generation and propagation process for SEMT are accurately modeled by use of "four logical value" and the signal probability. Thus effectively reduce the computational complexity and improve the speed of SER evaluation.Finally, as the integrated circuits are widely used in production and daily life, the reliability of the integrated circuits has become an increasingly serious problem. To accurately compute the SER of digital circuits, a SER estimation method considering SEMT is proposed. This approach extracted SEMT fault position pairs by parsing circuit netlist. By using a double exponential current source model, fault injection was simulated on a particle stroked gate. Further, SEMT pulses in a fault position pair were converted to an overlapped SET pulse by means of SEMT pulse composite model. By propagating the overlapped SET pulse to downstream gate cells along the data paths, logical masking, electrical masking and timing masking were jointly evaluated with the proposed SEMT pulse masking model. As a result, the overall circuit SER was precisely calculated by the proposed SER estimation technique. Experimental results show that the proposed technique is more accurate comparing with the similar method and the relative difference is only 2% comparing with Monte Carlo method, thus the proposed method is valuable to fault tolerance design of ICs.