Soft Error Modeling For Digital Integrated Circuits Of Communication Systems

With the development of technology and digitalization, an increasing number of digital integrated circuits(ICs) are integrated into electronic device of space communication and information systems. However, the digital ICs are sensitive to soft errors, including single event upsets(SEUs) and single event transients(SETs) induced by single event effects. Therefore, evaluating the reliability of digital ICs becomes an important issue.At present, the radiation effects are commonly evaluated by radiation test, which is expensive and difficult to evaluate the performance of digital ICs at the design stage. Thus, many researchers want to find out an appropriate approach to predict soft errors duing the design phase.Along with the development of technology, soft error rate(SER) increases as feature size decreasing and close proximity of devices. And these effects bring new challenges for soft error prediction, particularly in three aspects as following. Firstly, a single event strike may produce a charge cloud over a region that encloses several devices, that is the charge sharing effects, which will result in multiple bit upset. Thus, saturated cross section is greater than the physical layout size of a memory cell fabricated in deep submicron processes. Secondly, critical charge decrease with feature size decrease and operating voltage scaling, which causes that the phenomena of direct ionization from proton must be charactered in SEU prediction. Lastly, soft errors induced by SETs can no longer be ignored.This dissertation, mainly focuses on the three issues above in order to solve the new cases occurring in submicron microelectronic devices, includes the following works: 1) the estimation of the heavy ion induced upset cross section for sequential components fabricated in submicron processes; 2) the prediction of cross section induced by proton; 3) the fast SER calculation of combinational circuits fabricated in submicron processes.For the first issue, in chapter 3, a simple circuit-level simulation-based approach is developed to predict single event upset cross section. According to experimental results, upset cross section induced by heavy ion strike is more related to ion strike location than to physical layout for advanced SRAM. The affected distance is defined as corresponding distance from the drain junction to the strike location. Firstly, a photocurrent source model with affected distance considered is developed for performing single event analysis quickly and efficiently. Through this circuit-level simulation model, radiation effects can be shown as the SPICE-simulated curve of LETs versus the corresponding affected distances, which are used for upset cross-section prediction. Then, a simple model for cross-section prediction with layout and technology parameters considered is utilized in the prediction. The calculated results based on this method are in good agreement with experimentally measured results.For the second issue, in chapter 4, we extend the work of chapter 3 and propose a fine-grain cross section model to predict upset cross section for advanced SRAM in radiation environments. The proposed prediction model employs fine sensitivity coefficient to improve accuracy of prediction results at low-LET region. Besides, we propose an improved nuclear model for cross section induced by secondary ions generated from proton. And the calculated results based on the proposed models are in good agreement with experimentally measured results of SRAM fabricated in nano-metric process technologies.For the third issue, in chapter 5, a soft error rate analysis method for combinational circuits is developed based on hardware fault injection system. Based upon the analysis of single event transient propagation effects, both electrical masking and broadening effects could be illustrated as an analytical function according to gate delay. Through the analysis results, a SET emulator, with both electrical masking and propagation induced pulse broadening(PIPB) effects considered, is characterized through a linear counter and a comparator at logic-level for hardware emulation. Through the counter, delay information of a gate could be quantified to the same time unit. In addition, the propagation effects could be illustrated based upon comparactor threshold and counter maximum value. Experimental results indicate that the proposed approach achieves good accuracy compared to simulation-based method. The estimated single event rate for the ISCAS’85 benchmark circuit implemented in 130 nm technology is in the same order as compared to other algorithms.