Design Of High Speed And Soft Error Tolerant Arithmetic Units In 65nm Process

Microprocessor is one of the most important components of the electric system, while arithmetic units affect the performance of microprocessor greatly. Researches on the high speed arithmetic unit are very valuable in improving the performance of microprocessor. 64-bit high speed adder and shifter are designed in this paper. Simultaneously, high reliability is demanded for the microprocessor in some special occasion, such as space aeronautics. So, soft error tolerant adder is also designed. The work mainly contributes to the following aspects:1. A novel layout placement of the hybrid adder is proposed. Then, performance optimization of the design is carried out through logic simplification. And a much smaller area and higher frequency are obtained.2. We propose a high speed hybrid shifter, followed by logic design and layout design. The performance is improved with the area of layout acceptable. We research the logarithm shifter in 65nm process and obtain a valuable conclusion that it's not an advisable choice to design the high bandwidth shifter with the logarithm shifter in 65nm process.3. A soft error tolerant technology is presented based on the sound exploitation of inherent hardware redundancy and timing slack in hybrid adder. We implement a soft error tolerant adder, which could deal with 32-bit or 64-bit data. The simulation results show that our adder is immune from 85.87% of injected pulses in average. Furthermore, the area and delay overhead of our adder is small or less.64-bit high speed adder and shifter are designed in this paper. The simulation results show that the function is right and the performance is improved compared to conventional ones. And then we design soft error tolerant adder, of which the soft error tolerant capability is sound and overheads are small. The prospective achievement is obtained, and the work has certain reference significance.