Research On Several Effects Of SET In Combinational Circuits And Soft Error Rates Analysis

Recently, the rapid development of space industry brings out a higher request on the radiation hardened high performance integrated circuits. SEE induced by radiation is one of the key issues that determine the reliability of electronic components in space applications. With the feature size of integrated circuits scaling down, single event transient (SEE) in combinational logic gets increasing attention. The soft error rate induced by SET is becoming the dominant source in the total soft error rates. So it is very significant to study SET. In this thesis, we aim at the analysis of the soft error rates in combinational logic, and study the mechanism of SET generation and propagation. The main work and contributions of this thesis are as follows:1) We comprehensively study the effect of p-well contact on the n-well potential modulation in P+ deep well technology. It is found that the increasing p-well contact area will enhance the n-well potential modulation while the p-well contact location has little influence on it. According to our simulation results, it is proposed the small p-well contact area should be adopted to harden SEU and SET of PMOS in n-well. However it is a usual manner to restrain SEL and SET by increasing the well contact area. A tradeoff should be made for the circuit designer when the p-well contact area in the P+ deep well technology is designed to mitigate SEE.2) We propose that the guard drains should be used to replace the guard rings around NMOS to reduce the SET width. The guard rings around NMOS will reduce the amount of charge when the incident ions strike NMOS, but the guard rings will widen the SET width as the OFF PMOS is hit. So we proposed the guard rings should be replaced by the guard drains. According to our work, the guard drains around NMOS has no effect on the SET width. And guard drains will reduce more collected charge compared with guard drains when the OFF NMOS is hit.3) We propose a SET propagation method based on mixed-mode simulation for computing SER in combinational logic to solve the slow speed of SPICE simulation and the low precise of traditional methods in treating re-convergence. Results show that this method gains a close precision to SPICE. Based on this mixed-mode simulation method, we implement a soft error rate analysis tool for combinational logic. Compared with the prevalent used soft error rate analysis tool, it is shown that re-convergence occurred in combinational circuit will have a great impact on the SER in nanometer technology.