A 14-bit Analog-to-Digital Converter With On-Chip Self-Calibrated Reference Voltages For Remote Sensing Application

The CMOS image sensors dedicated to the aerospace industry need to have high sensitivity,wide dynamic range,high precision,and anti-irradiation.In this thesis,a 14-bit analog-to-digital converter(ADC)for self-correction of reference voltage for remote sensing detection is designed and designed for the high integration and high precision of CMOS image sensors.The chip uses two pairs of reference voltages reduces the area of the capacitor array and reduces the chip size.In addition,combined with the concept of correlated double sampling and successive approximation,an on-chip reference voltage self-correction algorithm is used to ensure accurate matching of the two pairs of reference voltages.The image sensor of this paper has a pixel array size of 160(column)× 190(row)and a frame rate of 300 frames/second,using the architecture of the column readout circuit.Designed four reference voltage successive approximation register(SAR)ADC mainly includes digital-to-analog converter(DAC),comparator and SAR logic,the input differential signal is ±2.4 V,the sampling rate is 600 kSps,the ADC quantized clock is 10.8 MHz,requiring a measured accuracy of 12 bits and a power consumption of no more than 700 ?W.The chip uses the Tower Jazz 0.18 ?m.3.3 V CMOS image sensor technology,and the DAC capacitor array uses Metal-Insulator-Metal(MIM).The unit capacitance is designed to be 8×9 ?m2,and the value is 75 fF.The reference voltage self-calibrated module is mainly composed of ADC,DAC and self-calibrated logic.VREF_BOT(0.4 V)and VREF TOP(2.8 V)are externally supplied reference voltages.The self-calibration module is used to ensure the accuracy of the two on-chip reference voltages VREF_BOT + VF/128? and VREF_TOP+VF/128(VF = VREF_TOP—VREF_BOT)and their matching with VREF_BOT and VREF_TOP.In this study,the self-calibrated algorithm is modeled using MATLAB,and the correctness and rationality of the algorithm are verified by simulating the calibration results under various non-ideal conditions.The final image sensor chip's size is 14705,5×7180.4 ?m2.The size of a single ADC is 2714.9×50 ?m2.The post-simulation results show that the ADC has effective bits of 12.7 bits and 12.2 bits at sampling speeds of 150 kSps and 600 kSps,respectively.The calibration results of the reference voltages self-calibration module are within ± 1 LSB.The sensor system is fabricated on the same die as the individual test ADC and calibration module,and the final chip is packaged in a 100-pin PGA.The ADC's measured static indicator DNL was +5.1/-1 LSB and INL was +5/-12 LSB.The effective bits are 11.7 bits and 11.1 bits at sampling speeds of 150 kSps and 600 kSps,respectively,meeting the basic requirements of design parameters.The two reference voltages's measured calibration errors of VREF BOT and VREF_TOP are 12.89 LSB and 8.18 LSB,respectively.