Design Of Analog-to-Digital Converters For High Performance CMOS Image Sensor

CMOS image sensors are widely used in consumer electronics,manufacturing research,military defense,and other fields.With the continuous development of CMOS image sensors,CIS integrated on-chip ADC arrays,which helps to improve system integration,enhance SNR,signal anti-jamming capability and the readout speed of CIS.At present,people have more demands on the performance of CIS,mainly focusing on high resolution,high frame rate,and high dynamic range.In this dissertation,the on-chip column-level analog-to-digital converters of CMOS image sensors are studied and designed,a column-level successive approximation ADC for CMOS image sensors is successfully designed.This dissertation designs a split capacitor SAR ADC based on the charge redistribution principle with the resolution of 14 bit and the maximum sampling rate of 10 MSPS.Since the on-chip column-level ADC of CIS is an array structure,the requirements for area and power consumption are quite demanding.However,in order to improve the resolution,it is necessary to increase the area of the capacitor;increasing the capacitance will increase the area of the ADC,increase the power consumption,and slow down the setup time;improving the accuracy of the comparator will further increase the power consumption.The core of the research CMOS image sensor on-chip integrated SAR ADC is to use an algorithm to overcome the capacitance mismatch in a limited area,and solve the problem of comparator noise,incomplete circuit establishment,and solve the contradiction between ADC accuracy,speed,area,and power consumption.This design uses 0.18?m 1P4 M CMOS technology,the overall chip area is 4700?m ×2000?m.A total of 64 column-level SAR ADCs are designed on this chip,the layout area of a single column-level SAR ADC is 760?m × 55?m.With a 1.8V supply voltage,the single-channel SAR ADC consumes 1.18 mW.When the sampling clock signal frequency is 10 MSPS and the input signal frequency is 4.873468675 MHz,the circuit simulation results show that the effective bit number(ENOB)of the SAR ADC designed in this thesis is 13.19 bit,the signal-to-noise and distortion ratio(SNDR)is 81.1dB,and the total harmonic distortion(THD)is-82.6dB,the spurious-free dynamic range(SFDR)is 82.8dB.The prelimanary test results of the chip shows that the effective bit number(ENOB)of the SAR ADC is 13.20 bit,the signal-to-noise and distortion ratio(SNDR)is 63.2dB,and the total harnomic distrotion(THD)is-69.9dB,the spurious-free dynamic range(SFDR)is 71.2dB.