Research And Implementation Of Fractional-N PLL

In the field of wireless radio frequency communication,the frequency synthesizer has played a pivotal role in the radio frequency chip,and the ?? fractional frequency synthesizer can be unrestricted in the output frequency resolution compared to the integer frequency synthesizer.The input reference frequency is set to a value which is much smaller than the reference frequency,and it can also be used for a wide range of advantages such as fast switching of the output frequency.The frequency synthesizer is essentially a self-control system based on negative feedback.It needs to take into account the noise characteristics of the system,the stability of the system,and the locking time of the system during design.However,these three characteristics often interact and interfere with each other,so the design The frequency synthesizer needs to comprehensively consider these several properties.This paper analyzes the small-signal model of the phase-locked loop,establishes the open-loop system function of the phase-locked loop,and obtains the closed-loop system function according to the negative feedback principle,and derives an integer-type phase-locked loop and a fractional-type phase-locked loop respectively.In each module,the noise contributed by the phase-locked-loop relational loop system is given,and the empirical formula of the loop bandwidth and the lock-in time is also given to establish the connection between these parameters.Each module in the integer and fractional phase-locked loops is fully explained,especially the analysis and principle explanation of the delta sigma modulator is studied in depth,and a simulation model based on SIMULINK is established.The formulas for the commonly used second-order and third-order loop filters are also deduced,and the formula for solving the filter parameters in the loop is deduced.In the phase-locked loop design,a fractional phase-locked loop structure based on the MASH 1-1-1 ?? modulator is used in this paper in order to suppress the spurious introduced by the ?? modulator in the loop bandwidth and the output sequence.In the periodicity,a linear shift register is introduced into the circuit to shake the carry ports of the last two stages of the ?? modulator.Experiments have proved that this technique can well suppress spurious at low frequencies and also eliminate ??.Modulator output sequence periodicity.Through the final simulation and performance evaluation of the system,the frequency synthesizer operating frequency is 1420MHz-1690Mhz two orthogonal output(ultimately required by the two frequency output 710M?845M),the smallest frequency step is about 396Hz,out of band The phase noise is about-122dBc@1MHz,130dBc@2MHz,and the overall power consumption is about 6mW.