Cmos Frequency Synthesizer For Wireless Communication, Research And Design

Wireless Communication has been hot in Radio Frequency Integrated Circuit (RFIC) research and design these years. As one of the key blocks in RF transceiver, Frequency Synthesizer (FS) comes into the research focus world widely. This thesis aims at the research and design of Phase Locked Loop (PLL) based Frequency synthesizers targeting at the wireless transceiver applications with standards such as GSM, WCDMA and IR-UWBFirstly basic concepts and architectures of PLL are reviewed and the model of PLL is introduced. Requirements of FS in the application of GSM, WCDMA and IR-UWB are derived.Design and optimization of PLL blocks are discussed in details. This thesis emphasize on the design of Charge Pump (CP), Multi Modulus Divider (MMD) and Sigma Delta Modulator (SDM). The influence of the CP on the spur and phase noise performance is investigated in theory and the point that dynamic mismatch dominate the mismatch effects of integer N frequency synthesizer is raised. Archetectures of MMDs are summarized. Phase shifting technique is used to realize a 7.5/8 dual modulus divider. The divide by 4 circuit is improved to avoid error function due to indeterministic initial phase. The noise shaping characteristic of the SDM is introduced and comparison between Multi Stage Noise Shaping Modulator (MASH) and single loop modulator is made. A 3-bit single loop modulator is used in the fractional N PLL.The Automatic Frequency Calibration (AFC) techniques are categorized and summarized. The factors that influence the resolution and speed of the AFC are discussed theoretically. A high speed high resolution AFC block is proposed, by eliminating the frequency divider in the AFC loop, the performance of the AFC is improved. The simulation results proved the technique effective.A 4224 MHz aimed for IR-UWB sub-sampling receiver is designed and verified in SMIC 0.13μm technology. Measurement results show the frequency synthesizer output frequency is exactly 4224 MHz, exhibiting phase noise of-94dBc/Hz,-96dBc/Hz and-114dBc/Hz at 10 kHz,100 kHz and 1 MHz, respectively. The rms jitter integrated from 100Hz to 100MHz is 0.57 ps and spur level is-63 dBc. In addition, a synthesizer for GSM/WCDMA application is also designed and the simulation results show the synthesizer meets the requirements of both standards.