Research Of Low Voltage CMOS Fractional-N PLL Frequency Synthesizer

The phase-locked loop(PLL) frequency synthesizer is a critical device in wireless communication system. For its advantages in high output signal spectrum purity, low power consumption and low cost in realization as well as application, PLL frequency synthesizers are widely used in RF wireless transceivers as local oscillator(LO) for frequency translatio n and channel selection. Nowadays, with the rapid development in mobile communication and the popularization in smart handheld devices, full integrated wireless transceiver SOC implemented in advance CMOS process has become the mainstream solution for low cost general purpose application. The trend in wireless transceiver design is to support mult imode communication and realize multifunctional application at the cost of lower power consumption and smaller silicon area occupation, which makes the design of low power low phase noise PLL frequency synthesizer with wide frequency tuning range to be necessary and inevitable. This dissertation is concerned with the design of low voltage PLL frequency synthesizer, especially the design of its key building blocks. The main contributions of this work are presented as follows.Firstly, the design method for PLL system is studied. Utilizing LTI model in S-domain, the loop stability and dynamic characteristics are analyzed in detail, which results in feasible loop filter design strategies. Meanwhile, the phase noise analysis model is obtained for integer/fractional-N PLLs, by which the PLL system can be optimized at the top-level design.General y speaking, the ordinary class-B VCO topology experiences obvious performance degradation under the low supply voltage condition. Although traditional class-C VCO topology is a more promising solution in theory, it exhibits serious risk in startup failure and sensitivity to PVT variations as well as frequency tuning. To solve these problems, this dissertation proposes a novel class-C VCO topology with two feedback loops. The first is a low frequency common-mode signal feedback loop, used for biasing cross-coupled pair transistors in class-C mode. And the other is an amplitude feedback loop for LC-tank amplitude constant. This novel VCO also implements a time varying tank bias current in startup, which endows our design with very robust class-B VCO like startup and good power efficiency in steady operation. Besides, it facilitates a direct amplitude calibration method to find optimal point for different applications. A dual-loop feedback class-C VCO prototype chip is implemented in a 0.18 μm CMOS process. Measurement shows the VCO has a 4.55-5.16 GHz frequency tuning range and a phase noise of-123.3 d Bc/Hz at 1 MHz offset from a 5 GHz carrier. This VCO core circuit consume 2.78 m W power form a 1.5V supply, this leads to a figure-of- merit(FOM) equal-192.8 d Bc/Hz.This dissertation also proposes a charge pump with programmable output current for low voltage design. It consists of two sub-units both of which leverages replica bias and feedback control techniques to achieve perfect match between charging and discharging output currents. With the help of current summing structure, the output current variation in each sub charge pump can be compensated by the other. Thus, their sum current retains relative ly constant in a wide output voltage range. The charge pump can be programmed to output 50 μA-1.55 m A current, with a 50 μA minimum step. It is designed in a 0.13 μm CMOS process and the post-layout simulation demonstrates the total current mismatch and variation rates are limited in 0.15 % and 5 %, over the output voltage range 0.1-1.05 V with 1.2V supply voltage. Such precise matching greatly suppresses the reference spur and loop nonlinear it y due to charge pump, and the good current constancy is favorable for dynamic design. Both features render this design suitable for low voltage PLLs.The analysis and design about other key modules in PLL frequency synthesizer are also discussed in this dissertation such as: PFD, digital ΔΣ modulator, programmable divider, N/N+1 prescaler and so on. Finally, based on above works, a fractional-N PLL frequency synthesizer prototype is implemented in a 0.13 μm CMOS process and occupying a chip area of 1.68mm2. The frequency tuning range of the dual-loop feedback class-C VCO in this design is 4.4-5.4GHz. After dividing the VCO output by 2 through high speed CML divider, the frequency synthesizer produces quadrature I/Q LO signals from 2.2-2.7GHz. A MASH 1-1-1 digital ΔΣ modulator is designed to obtain dynamic frequency division ratio for fractional-N operation. With a 1.2V supply, measurement shows the prototype chip consumes 12.5m W power and, across the required output frequency range, the phase noise at 1MHz frequency offset from the carrier is always lower than-122 d Bc/Hz. In addition, the measured spur result including reference spur and fractional spur is never higher than-70 d Bc.