Research Of Fractional-N PLL Frequency Synthesizer Based On CMOS Process

The Phase-lock loop(PLL)frequency synthesizer is mainly used for generation of the carrier of the signal in Radar and the wireless communication system.Thus,the performance of PLL is directly related to the accuracy of the data modulation or demodulation in transceiver system.Additionally,there are some stringent requirements for the speed of channel switching and the range of frequency scanning in Radar Data Communication.Thus,high performance PLL with wide output range,low phase noise and fast locking are the new trend and research hotspot in the field of analog integrated circuit.Based on the CMOS process,this thesis is concerned with analyses of the whole system and the concrete realization of each module.First and foremost,this paper expounds the key technologies of circuit design and the relationship between performance parameters and basic module from the development course,type classification and basic principle.Supposing the output current is continuous,the linear time invariant s-domain of PLL is established to analyze the dynamic characteristics and stability of the loop.Furthermore,the order interrelationship of the loop filter and digital delta-sigma modulator can be obtained.By the requirements of ku-band radar,the main design performance indexes of each essential part in PLL frequency synthesizer.Secondly,this thesis has carried out the conventional architecture and composition of Phase Frequency Detector(PFD).The proposed PFD circuit is constituted with the dynamic D flip-flop and the programmable delay circuits,which can effectively implement the basic function,and have low power consumption and better noise performance.In many published works,the matching of CP output current is improved by an operational voltage amplifier,which works in deep negative feedback state to"clamp voltage".A programmable CP structure is used in this works for the wider applications.In order to optimize the phase noise of VCO,this thesis proposes a novel class-C VCO topology with voltage feedback loop,which can improve the reliability of oscillation.Meanwhile,the design procedure of the parameters of each electronic device from the performance requirements is explained in detail.Then,the design about programmable divide with wider frequency division ratio is discussed in this thesis based on the principle analysis of premade four frequency division,digital??modulator,programmable divider and N/N+1 prescaler.Finally,the design of PLL frequency synthesizer is verified by the layout and simulation results.Based on above works,a fractional-N PLL frequency synthesizer prototype is implemented in a TSMC65nm 1P9M process,power supply voltage is 1.2V,core chip layout area with PAD is1933 m×1552 m(3.00mm~2).The center frequency of PLL is 15GHz and the output frequency range is 13.5GHz~17.5GHz with 6-bit switching capacitor array,the lock time is less than 50us.For high frequency working state,the phase noise at 1MHz frequency offset from the carrier is lower than-106.22dBc/Hz@1MHz and phase noise is lower than-110.8dBc/Hz@1MHz when the frequency of PLL is low in the different process corners.