Research And Circuit Design Of Noise Folding In Fractional Frequency Synthesizer

There are many different Digital-TV standards around the word, and the next generation standards is published for the delivery of innovative new services like high definition television (HDTV), it brings many challenges for the frequency synthesizer of the RF receivers. The synthesizers must support a wide range frequencies and stringent Phase Noise requirement. However, it is well known that the performance of fractional-N frequency synthesizers is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise. This thesis aiming at linearization technique, divider chain and reduction of phase noise especially in-band phase noise.The review of Charge Pump frequency synthesizer and four main fundamental figures of merit is present. The phase noise model of ΣΔ fractional-N frequency synthesizer is used to analysis the mechanism of noise-folding phenomenon. A detailed theoretical derivation is done to figure out the principle of out-band quantization noise transferring to the in-band phase noise due to the circuit nonlinearity.According to the detailed analysis of the noise-folding phenomenon, a linearization technique is proposed and a modified PFD circuit is designed to solve this problem without raising the reference spurs. A Divider Chain with frequency division by a factor of2or its power such as4/8/16is realized to extend the frequency coverage, and quadrature I/Q signals with excellent phase noise performance is obtained at same time.Based on the previous theoretical analysis and some techniques, a ΣΔ fractional-N frequency synthesizer was fabricated in a0.18μm CMOS process with a total power consumption of36mW from a1.8V supply. The die area is840μm×970μm. The in-band phase noise of the synthesizer is-107dBc/Hz at10kHz offset, the in-band phase noise is more than10dBc/Hz better than the one with the noise-folding problem. The integrated rms phase error is below0.6°, the worst reference spur is below-74dBc when using the proposed PFD and the worst IRR is45dB without any calibration and the locking time is less than30μs.