Design Of Key Modules Of Fractional-N Frequency Synthesizer In Wireless Receiver

In this thesis,a fractional-N frequency synthesizer with low-power consumption and high-performance is designed for short-range wireless receivers used in the field of wearable medical devices.A detailed and thorough study on the design of the fractional-N frequency synthesizer is carried out from the aspects of theoretical analysis and modeling,system and specifications design,specific circuit and layout implementation,functional simulation and verification.Firstly,the basic principles of phase-locked loop?PLL?are introduced,including the classification,the working principles,the component modules,and the design specifications.The basic principle of each component module and its role in PLL were analyzed.The linear loop model of PLL is given.The PLL is summarized at the level of the whole system.Secondly,the fractional frequency divider in fractional-N frequency synthesizer is analyzed and designed.The principle and design method of?-?modulation technology is introduced,and the behavior of?-?modulation is abstracted and modeled.The structures and principles of several different high-order?-?modulators are analyzed,and the performances of these high-order?-?modulators is compared by means of simulation behavioral model in Simulink,including the stability,the noise shaping capability,and the output sequence randomness.An SS-FF33 structure is chosen according to the result.A digital circuit realization method is given,and functionality is validated with Modelsim.Then,the discrete-time sampling system model is used to model the fractional-N frequency synthesizer,based on the linear loop model of the PLL.In particular,the discrete sampling behavior of phase&frequence detector?PFD?and frequency divider are analyzed.The model is the basis for understanding and analyzing the noise transmission model of the?-?modulator and also the premise of modeling the noise characteristics of the fractional-N frequency synthesizer.Through the analysis of the model,a more realistic mathematical model of the PLL system is obtained.According to the system specifications of the short-range wireless receiver,the specifications of each module of the PLL fractional-N frequency synthesizer are planned,and the design method of the loop parameter of the phase-locked loop is analyzed and summarized.In particular,the relationship between the loop parameters of the 3^rd-order loop filter and the specifications such as phase margin,the loop bandwidth and the noise characteristics are analyzed.A design scheme for determining the resistance and capacitance parameters of the 3^rd-order loop filter is proposed.According to this design scheme,a Matlab script which can automatically calculate the resistance and capacitance parameters of the third-order loop filter is completed.According to the determined loop parameters,the design of each specific circuit module,including the voltage-controlled oscillator?VCO?,the PFD,the charge pump and the frequency divider circuit is carried out in detail from the aspects of working principle,structure selection,design analysis,and functional simulation,etc.The VCO uses a 4-stage ring oscillator to achieve quadrature signal output.The charge pump uses a servo loop and current steering structure to achieve good current matching.The prescaler uses a true-single-phase-clock?TSPC?structure which has lower power consumption while operating speed requirements are still met.Finally,the layout of the fractional-N frequency synthesizer is designed using a SMIC 0.18-?m CMOS process.The layout parasitics are extracted and the circuit is post-simulated.Among them,the digital part such as?-?modulator adopts Design Complier tool to carry on synthesis and uses Astro tool to finish automatic placement and wiring.According to the simulation data,the noise characteristics of the fractional-N frequency synthesizer are modeled and calculated,and its phase noise performance is analyzed.The result of the simulation proved that the fractional-N frequency synthesizer realized a high-precision local oscillator signal output with the frequency resolution of 10kHz and power consumption of 3.5 mW.The output phase noise is less than-100.3 dBc/Hz at 1 MHz offset and the lock time is less than 15?s.The specifications of simulation results satisfy the expected design requirements.