Design Of Sigma-Delta Modulator And Programmable Frequency Divider In Fractional Frequency Synthesizer

In modern sophisticated electronic systems,especially in communication systems,radar,electronic countermeasures,the application of frequency synthesizers is extremely widespread.With the maturity of information technology,electronic systems continue to develop in the aspect of compact size,high performance and low cost.The development of frequency synthesizers is one of the key links.The main function of the frequency synthesizer is to provide the required local oscillation frequency for the RF transceiver,and it can also provide the clock frequency that some digital systems can use.There are many kinds of frequency synthesizers,among which PLL frequency synthesizer is the most popular one.Therefore,this project is also based on this structure.Programmable frequency divider is introduced into the feedback loop of PLL circuit to achieve different frequency ratio,and then controls the output frequency of the whole system.Due to the limited frequency resolution of the integer frequency synthesizer,the fractional frequency division technology is applied here.In order to reduce the fractional spurious,the sigma delta modulator is utilized on the basis of the fractional frequency division to improve the noise performance of the system.The dissertation first introduces the background and significance of this project,and investigates the research status of frequency synthesizer and related modules.Then the principle of frequency synthesizer,sigma delta modulator and programmable frequency divider is analysed.In the design of sigma delta modulator,the structure and performance of single-order sigma delta modulator are discussed in detail.In addition,the high-order structure is put forward and improved,together with the verification of the improved structure by model simulation.Due to the system requirements,the programmable frequency divider is composed of three types of frequency dividers: the cascaded structure of 2/3,4/5 and 8/9dual-mode frequency dividers,with the pulse swallowing counter structure based on the pre dual-mode prescaler.The design process of three frequency dividers and other auxiliary circuits is illustrated at full length here.Finally,the layout design and simulation verification of sigma delta modulator and programmable frequency divider are complished.The schematic and layout design is implemented in the 0.18μm BiCMOS process.Moreover,the function and performance verification of sigma delta modulator and programmable frequency divider are demonstrated in the dissertation.The fabrication of the flow chip and chip testing is completed,and the test results meet the design requirements.