A Study On Key Techniques Of 12-bit Multichannel Time-interleaved A/D Converter

In recent years,with the rapid development of 5G mobile communications,high-resolution instrumentation and other fields,the demand for high-resolution ultra-high-speed analog-to-digital converters(ADCs)has been increased.The sampling rate of a single-channel ADC has been difficult to be rapidly improved with the progress of integrated circuit process,but this problem is solved by the time-domain interleaving technique that can effectively improve the ADC's sampling rate.Time-domain interleaving technology keeps multiple parallel channels work alternately by multi-phase clocks,thereby multiplying the sampling rate while ensuring accuracy,which becomes an inevitable technique for ultra-high-speed ADCs.Nevertheless,there are still many key technologies that need to be further broke through due to the demand for accurate sampling control clock for time-domain interleaving technology.The time-domain interleaving technique makes a trade-off with the accuracy and power consumption in the process of improving the sampling rate of ADC.Therefore,it is necessary to carefully design the ultra-high-speed time-domain interleaving ADC to reduce the accuracy deterioration and power consumption.The optimization of single-channel pipelined ADC is performed in this thesis,which includes the following three parts:The high gain wideband operational amplifiers are implemented by using transconductance enhancement technology,so the power consumption of amplifiers is reduced while design requirements are satisfied;The effects of the sampling transistor's body effect and the parasitic nonlinear diode capacitance are eliminated in the designed bootstrapped switch,improving the linearity;A high-speed comparator with low offset voltage is implemented by the input offset voltage storage technology and the architecture of combination of two-stage pre-amplifier and latch.And then a 12-bit,500MSPS,single-channel pipelined ADC is finally implemented.Based on the TSMC 65nm CMOS process,the design of whole circuit and verification of layout are completed.The layout area of the designed single-channel,12-bit,500MSPS pipelined ADC is 0.65?1.15 mm~2.When the input signal is a sinusoidal signal with frequency of 20MHz and swing amplitude of 1.6V,the post-layout simulated results show that the signal to noise and distortion ratio(SNDR)is68.43dB and the effective number of bits is 11.07bit.Then the non-ideal effects introduced by time-domain interleaving technique are analyzed in detail in this thesis,including offset voltage mismatch,gain error mismatch,and sampling time mismatch.Moreover,the corresponding correction methods are introduced.At the same time a method for correcting the mismatch error of the sampling time in the analog domain and a digitally controllable delay unit in the analog domain used in an mixed domain correction are given.In order to reduce the large load effect and coupling effect of the interleaving ADC on the pre-drive,an optimized input buffer circuit is given and the designed on-chip bandgap reference circuit is also presented.Based on the TSMC65nm CMOS process,a 12-bit 4GSPS interleaving ADC is finally implemented and the layout is completed with total area of 3.16?4.05 mm~2.When the input signal is a sinusoidal signal with a frequency of 20MHz and a swing amplitude of 1.6V,the post-layout simulated results show that the designed eight-channel interleaving ADC achieves an SNDR of 64.52dB and an effective number of bits of 10.43bit.