Research And Design On Input Network Of Ultra High Speed And High Resolution Analog-to-Digital Converter

In the real world,signals are almost analog signals.But digital signals are more widely used in modern electrical technology.In order to translate analog signals to digital signals,analog to digital converts(ADCs)are needed.As the communication system has entered the 4G era and the 5G era is coming,and the satellite communications are developing,the requirements on the speed and resolution of ADCs are higher and higher.The input network is the interface between ADC and the outside world.As it is the first module to deal with the input analog signals in ADC system,its speed and resolution limit the performance of ADC system.Therefore,ultra high spe ed and high resolution ADC design should start from the design of ultra high speed and high resolution input network.In this paper,the design of the input network covers the buffer theory,the sample and hold circuit and the multi channel time interleaving theory.The input network of ultra high speed and high resolution ADC is implemented in the 65 nm CMOS process.With the 2.5GHz sampling signal and the Nyquist frequency input signal whose difference signal amplitude is 1.2V,the SFDR is higher than 60 d B.The output of input network could be quantized by subsequent circuits.The research results of this paper are as follows:1.This thesis compares the different architectures of the input network,analys their application.In the case of ultra high speed and high resolution,the structure of multi channel time interleaved with input buffer is chosen finally.2.The theory and structure of buffer circuit are researched.Analyse the source of nonlinearity and the method to improve it.A high speed buffer is designed which based on source follower structure.3.The circuit and structure of sample and hold circuit are studied.Analyse its no n ideal factors and the methods of improving the speed and linearity.The S/H circuit is implemented based on the open loop structure.4.This paper studies the input network of the multi channel time interleaved ADC.Analyze the mismatch of multi channel architecture and design a sign-equality digital calibration technique for the timing mismatch.Design and verification of ultra high speed and high resolution input network based on 65 nm CMOS process.With a 2.5GHz sampling frequency and the Nyquist input frequency signal whose differential signal amplitude is 1.2V,the SFDR of this work is 72.52 dB.With the low input frequency,the linearity of the input network is higher than 80 dB.At the condition of a timing mismatch(?T=1%T_S)on clock generator,when the digital calibration work,the linearity of input network is increased from SFDR=44.26 d B to SFDR=70.83 dB.The result is close to the linearity of the output signal without the timing mismatch.The sign-equality-based digital calibration algorithm eliminates the influence of timing mismatch on the linearity of input network.