Research On MDAC In High Speed And High Precision Pipelined ADC

Various analog signals in our environment,such as sound,light and electrical signals are real and we can perceive them intuitively,while digital signals are not intuitive and are abstracted and need to be interpreted through logic,in order to facilitate our processing and storage of information with the help of computers.But the analog world and the digital system cannot communicate and transform directly,we can resort to Analog to Digital Convertor(ADC),which is the key module for digital signal processing in modern communication systems.Entering the new century,the advancement of 5G wireless communication network technology has led to the rapid development of mobile Internet,and various devices have more stringent requirements for communication speed and information quality,increasing the demand for high-performance ADCs,thus promoting the rapid development of high-performance ADCs.With the shrinking transistor size,high-performance analog-digital hybrid integrated circuits encounter more and more difficulties,especially the reduction of MOS device intrinsic gain and the increasingly low chip supply voltage in advanced processes,analog integrated circuit design is becoming increasingly difficult.ADCs with a pipelined architecture have many advantages,being able to take into account the accuracy of signal conversion at a higher operating speed and having a better compromise between power consumption and performance,so a pipelined architecture is used to implement high performance ADCs as a way to adapt to different needs.MDAC(margin gain module)is the key component of pipeline ADC,which largely determines the performance of the converter,so this thesis will introduce and analyze the MDAC circuit of pipelined analog-to-digital converter in detail.The main work of this thesis is to complete the design of MDAC for each level in a high-speed high-precision pipelined ADC in a 40 nm CMOS process.Firstly,the basic principle and main parameters of the pipelined analog-to-digital converter are described,then the basic principle and working process of the MDAC of the pipelined analog-todigital converter are analyzed,followed by the analysis of the sample-and-hold circuit,the sub-modular converter and the non-ideal factors in the MDAC.Based on the analyzed non-ideal factors,redundant bits and op-amp output amplitude halving techniques are used in the design of the MDAC.Finally,through the system analysis of the 14-bit highspeed pipelined analog-to-digital converter,the main architecture is determined to be a SHA-less(sample-hold circuit-free)six-stage pipeline structure,with the first to fifth MDAC effective bits being 3 bits and the last stage being 4-bit FLASH.the noise requirements of each module and the size of the sampling capacitor are determined through the noise analysis of the MDAC as a whole.The MDAC adopts a charge redistribution type structure with a 1.6p sampling capacitance in the first stage and a stepby-step reduction in the latter stage,and a two-stage operational amplifier with gain bootstrap in the amplifier.The overall layout area of the pipeline ADC completed in this thesis is about 902um× 407 um,and the power consumption is about 700 m W.Through the simulation after the layout,the reduced output signal SFDR is greater than 76 d Bc and ENOB is greater than11.5bit at the sampling rate of 1GSps,full swing signal input of 1.6V,and input signal frequency less than 1GHz.