| Analog-to-digital converter(ADC),as a key design module in modern microelectronic communication systems,has been highly valued by academics and industry.In recent years,with the rapid development of 5G mobile communication,the requirements for high-speed and high-resolution ADC have become higher and higher.However,due to the relatively late start of relevant research in the field of high-speed and high-precision ADC in China,the current domestic research and development level are far below the international advanced level,especially recently influenced by the international situation,which reflects the urgency of speeding up the independent research and development of high-performance core chips in China.Among many ADC architectures,pipelined ADC has become one of the best choices for high-speed and high-resolution due to its good compromise in speed,resolution and power consumption.Therefore,this paper focuses on the key techniques of high-speed and high-resolution pipelined ADC.In this paper,the basic working principle and redundant bit algorithm of the pipelined ADC are described,and the non-ideal factors of circuit and the main performance parameter of measuring ADC are discussed.Then based on the above content,from the system point of view and following the optimization of power consumption,the overall framework of ADC,the system noise allocation scheme with thermal noise far lower than the quantized noise,and the use of SHA-LESS circuit to reduce power consumption,noise and non-linearity are determined respectively.Finally,the speed factor and the reduction factor are introduced to optimize the system noise model,and the size of the sampling capacitor per stage is determined based on the system thermal noise requirement and this noise model.In this paper,a 12-bit 1GS/s pipelined ADC is designed and implemented based on TSMC65nm CMOS process,and the key circuit modules are studied and improved,including:a novel MDAC structure is adopted by using a separate DAC capacitor to reconstruct the signal to eliminate the kickback noise and the MDAC residual amplification factor in this stage is halved to solve the problem of small feedback coefficient of the opamp,which is designed in low-voltage working environment to reduce the overall power consumption of the system;the traditional input buffer is improved by adding feedforward replication capacitor,using switched capacitor circuit to achieve signal follow,adopting cascode structure and deep N-well special process to improve linearity;the traditional bootstrap switch circuit is improved by adopting the new dynamic driving DNW technology,adding the body effect elimination technology and reliability circuit;the traditional gain-boost amplifier is improved by introducing the transconductance enhancement technique of level shift,adopting the double tail current source structure,and using cascode compensation technology;this structure of comparator is improved by using double capacitance to sample the input and reference levels respectively,adopting multi-stage preamplifier and latch to realize the requirement of high speed and low offset.Finally,the whole ADC is simulated and the layout is completed.The overall layout effective area of the 12-bit 1GS/s pipeline ADC designed in this paper is2.10×1.04mm~2,and the overall power consumption is about 520mW.The pre-simulation results show that when the input signal frequency is 18.55MHz,SFDR of the ADC is80.50dB and SNDR is 72.25dB.When the input signal frequency is increased by487.30MHz,SFDR of the ADC is 77.56dB and SNDR is 70.10dB.The post-simulation results show that when the input signal frequency is 18.55MHz,SFDR of the ADC is75.88dB and SNDR is 67.32dB.When the input signal frequency is increased to487.30MHz,SFDR of the ADC is 71.16dB and SNDR is 64.61dB.The error in pre-simulation and post-simulation is mainly due to the influence of parasitic resistance and capacitance in the layout,but the overall linearity decreases little and is within the scope of theoretical expectation.The above results show that this design meets the design requirements of high-speed and high-resolution ADC. |
