High Performance Pipelined Analog To Digital Converter Design

Analog to digital converter (ADC), as the interface between the analog world and the digital world, is one of the most important parts in the modern communication system and system on chip (SOC). However, the rapid development of software defined radio, cognitive radio and multiple-standard high-speed communication system requires that the ADC should be compatible with a variety of communication system protocols and accommodate different signal bandwidths and dynamic ranges with minimal power consumption. This thesis researches on high performance pipelined analog to digital converters and focuses on the power budget of operational amplifier, programmable techniques and the source follower which acts as high-speed analog input buffer. The contributions of the dissertation are as follows:The complementary recycling folded cascode (CRFC) operational amplifier is proposed. The CRFC operational amplifier can save up to 60% power consumption compared with conventional folded cascode operational amplifier. The gain-bandwidth product (GWB) of the CRFC is 2.6 times larger than the conventional folded cascode operational amplifier with the same bias current. To increase the power-on speed and reduce the operation power consumption, a novel pre-charged switched operational amplifier is proposed. The power can be reduced by 32% when the operational amplifier is shut down in the sampling phase.An improved current modulated power scaling (CMPS) technique is proposed. The sampling rate can be adjusted without scaling the bias current of the operational amplifier. A novel sampling precision strategy is adopted to reduce the power consumption when the sampling precision is low. A 1.8V programmable ADC, which can achieve a conversion precision of 8 to 11 bits and a sampling rate from 400KS/s to 40MS/s without adjusting the bias current of operational amplifiers, is described.A CMOS source follower, which can eliminate body and channel length modulation effects, provides high linearity and high power supply rejection ratio. The experimental results show that the spurious free dynamic range (SFDR) is 80.4dB.A 12b 40MS/s calibration-free pipelined ADC, which is optimized for high SFDR performance and low power dissipation, is designed. The ADC presents 83.38dB SFDR at a 4.9MHz analog input and 40MS/s sampling rate, and the power consumption is 102mW from 1.8V supply. Furthermore, a 14b 100MS/s pipelined ADC has been designed and the preliminary test has been completed. With an analog input frequency of 4.9MHz, the SFDR is 80.3dB and 76.2dB at sampling rates of 15MS/s and 90MS/s, respectively.