Research And Design Of A 3-6GHz Wideband Phase-Lock Loop

With the explosive growth of wireless communications users,phase-locked loop,one of the hotspots in the wireless communication technology,has made great progress.This text focuses on the theory,modeling,system design and circuit of charge pump phase-locked loop.We set up a charge pump phase-locked loop noise model by Verilog-A after analyze the theory of charge pump phase-locked loop.The simulation results of the model is similar on system and the simulation time is short,This can greatly improve the efficiency of the follow-up work.Many system parameter design methods of fourth order charge pump phase-locked loop is not accurate by excessive approximation.This led to a big difference on the system stability and design of actual charge pump phase-locked loop.In this paper,we presents an accurate system parameter design method of fourth-order charge pump phase-locked loop.In this paper,We design a kind of constant K_VCO voltage-controlled oscillator and an improved frequency divider circuit in the charge pump phase-locked loop circuit.The constant K_VCO voltage-controlled oscillator is designed to reduce the phase noise of charge pump phase-locked loop.By deduced the linear function of C<6:0>to adjust the weights of fixed capacitor array with improved varactor circuit,we limit the K_VCO rate to17%.When the frequency divider ratio changes,the frequency divider could experience a few redundant states,which greatly reduces the precision of the frequency divider.Through deduced all the states of frequency divider,We find out the two Shared states which Can completely eliminates redundant states.The design of fourth order charge pump phase-locked loop uses TSMC 0.13?m1P6M process.Its frequency step is 50MHz,output signal frequency range is for 3-6GHz,phase noise reaches-88.9 dBc/Hz@10 kHZ and reference-spur is-64 dB.