Design Of A CMOS Charge-Pump PLL And Investigation Of The Phase Noise

With the development of the integrated circuit technology, the PLL (Phase Locked Loop) obtains more and more attention. CPPLLs (Charge-Pump PLL) become the mainstream and play an important role in VLSI and SoC (System on Chip) because of the merit of smaller phase difference and bigger capture range.This thesis designed a CPPLL which was based on CMOS technology and adopted top-down method. Firstly, the VHDL-AMS behavioral modeling of the close-loop system was designed based on the fundamental of CPPLL and the characteristic of VHDL-AMS language. Then, phase frequency detector, charge pump, loop filter, voltage controlled oscillator, divider and the clock distribution circuit were designed under the guidance of the behavioral model and the specification of the application system. Phase noise and jitter were analysed and simulated on the model. Finally, the layout was designed and taped out.The D/A converter including the CPPLL which was designed by this thesis has been fabricated in MPW based on the CMOS 0.35um 2P3M technology and passed the preliminary tests. The actual PLL circuit supports frequency division of 4～32, and outputs clock signals of different frequency. The power supply is 3.3V, adjustable frequency range is 96～400MHz. The power dissipation is less than 45mW, and the noise is less than 100dBc/Hz.