Research And Design Of Ka-band Low-phase-noise Phase-locked Loop

With the rapid development of integrated circuit,PLL plays an indispensable role in many fields such as wireless communication,radar,and computer applications.Charge pump phase-locked loop has become the mainstream of current phase-locked loop design in Very Large Scale Integration Circuit(VLSI)and system-on-chip because of its low power consumption,high precision,and low jitter.This thesis starts with the introduction of principle,circuit structure of each component of phase-locked loop;And then the impact of the phase noise of each module on the phase-locked loop circuit is analyzed;Finally,a phase locked loop circuit with low phase noise in the Ka band is achieved based on the power consumption,accuracy,lock time,stability and other performance.This paper uses a top-down design method to study the model and indicators of the phase-locked loop circuit from the system level,and then transition to the design of the circuit structure of each module and the simulation of performance indicators.Finally,a phase-locked loop circuit with an output frequency of 28G-35 G is designed.The power supply voltage is 1.2V,the phase noise is-91 d Bc/Hz@1MHz at 28 GHz.The phase noise of the voltage controlled oscillator is-102 d Bc/Hz@1MHz.A high-speed and high-precision phase detector composed of D flip-flop is adopted in the circuit structure of PLL;the charge pump of operational amplifier structure can eliminate charge sharing and clock feed-through effect;the second-order low-pass filter is used to eliminate voltage ripple,especially the voltage controlled oscillator structure with resonance switch technology and current multiplexing is used to realize low-phase noise in high-frequency range;A complementary differential input signal as its input and adopts a prescaler structure are used in the frequency divider to achieve a wide band injection-locked frequency division.Cadence spectrum tool is selected in this paper to design and simulate the circuit based on TSMC CMOS 65 nm model.The simulation results show that the design of each module and the whole PLL circuit meet the expected design requirements.