The Research And Design Of Fast Lock Charge Pump Phase Locked Loop

A new fast lock Phase Locked Loop (PLL) typology is presented in this thesis. The topology was then verified using Verilog-A behavioral model and implemented in TSMC0.18μm technology.This thesis first made theoretical analysis of stability, lock time and phase noise of Charge Pump Phase Locked Loops (CPPLL). Then relationship between loop bandwidth and lock time is studied which forms the foundation of loop bandwidth and lock time tradeoff. Top-down design approach was adopted in this thesis, fast lock CPPLL was first verified in Matlab-Simulink environment, and then implemented in Cadence Virtuoso environment.The innovation point of this thesis is the fast lock CPPLL typology. Both currents of charge pump (CP) and bandwidth of loop filter were designed to be adaptive. When the PLL is out of lock, both charge pump current and filter bandwidth are increased to achieve fast lock; once the loop is locked, both charge pump current and filter bandwidth will be reset to guarantee the non-deterioration of PLL phase noise. This thesis designed a new circuit to generate control signal of charge pump and loop filter. Different typologies of phase frequency detectors (PFD) and charge pumps were compared, and tradeoffs were made in power consumption, speed and area. The voltage-controlled oscillator (VCO) was designed according to the gm/ID methodology and three different inversion layers of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), which reduced the MOSFETs current and power consumption.The design was based on TSMC 0.18μm process. Simulation results show that the lock time of proposed CPPLL is 4.29μs, which is 38.8% save compared to a reference PLL that did not use fast lock typology. The total power consumption is about 15mW. The phase noise performance was not deteriorated visibly, which is-91.72dBc/Hz at 1MHz offset frequency.