The Study And Realization Of 12bit 200MS/s Pipelined ADC

As the bridge of Analog signal and Digital signal,the analog-to-digital converter(ADC)has been widely used in radar,wireless communication system,and other electronic information systems.With the rapid development of modern digital communication technology,in many structures of ADC,Pipelined ADC has become a mainstream architecture because of its good trade-off between speed,accuracy,power and area.The work of this paper is to study and design a 12-bit 200Ms/s high speed and high precision pipelined ADC.This dissertation paid more attention on the theory of pipelined ADC,source of error,circuits and layout.The main research work is as follows.: 1)Based on the main error source of pipeline ADC,the system framework is determined by using the low power consumption technology of Scaling down.The overall architecture is comprised of 7 stages circuits: It consists of a sample-and-hold circuit +5 stage 2.5-bit/stage current stage and the last 2-bit flash ADC.2)we created a mathematical model description of the pipelined ADC system and the irrational characteristics of the circuit with the matlab's simulink module.The effect of the limited gain / limited bandwidth of an op amp and the non-ideal characteristics of capacitor mismatch on the performance of the system were studied.3)The jitter of clock and the distortion of clock cycle have great influence on the dynamic performance of high speed ADC.In this paper,a built-in fast locking high precision low jitter DLL circuit is designed to provide low jitter clock for ADC.4)On the basis of the above,the 12-bit pipelined ADC circuit is designed by using TSMC 0.18?m 1P4 M CMOS process.The sampling-holding circuit adopted capacitor-flip structure to reduce noise and the power consumption.A gain-boosting op amp has been used to insure the requirement of large gain and bandwidth.A boostrapped switch has been used to reduce the harmonic distortion caused by the sampling process and to improve the linearity of the circuit.Besides,the application of preamplifier dynamic lock comparator can realize fast comparison and reduce kick-back noise.5)The circuit design and circuit simulation,layout design and layout verification have been completed.At the same time,the chip test scheme is designed,and the related performance indexes are tested.The results of the chip test are as follows: At 200MS/s sampling frequency,1.8V supply voltage,70 MHz input signal.The converter achieved 63.5dB of SNR,63.4dB of SNDR,80 dB of SFDR,10.3bit of ENOB,and a power consumption of 670 mW,a active area of the ADC is 3.74mm*3mm.