Design And Realization Of 12Bit 100MS/s Pipelined ADCs

With the continuous improvement and development of integrated circuit technology and digital signal processing, the realization of electronic system relies more and more on the digital way, especially on the image, video and wireless communication areas which SOC plays a powerful role. However, the analog IP becomes the bottleneck of performance improvement when digital design becomes more and more important in an SOC chip. In the interface analog IP aspect, it is very difficult to design an analog-to-digital or digital-to-analog converter that has high speed and high resolution simultaneity. Since the pipeline topology ADC can make a better compromise between high speed and high accuracy, it becomes the first choice for designing high speed and high precision ADC.Based on SMIC 0.13μm MS technology, a 12 bit,100 MS/s high speed Pipelined ADC is designed and realized. The chip is comprised by 12 stages:the first stage is sample-and-hold circuit, followed by ten stages, each contributes 1.5 bit resolution, and the final stage is a 2 bit Flash ADC. The Gain-boosted signal stage telescopic operational amplifier is used in the circuit to fulfill high bandwidth and high gain simultaneity without consuming large power. The bootstrap switch is introduced to ensure the linearity, and thus improve the dynamic performance. A substrate biasing effect attenuated T switch is proposed, thus, a high linearity on-resistance can be assured, and the T type structure makes the input-dependent signal feed-through effect neglectable. The bottom plate sampling technique is used to reduce the coupled noise due to signal transmission. Dynamic comparator is implemented to ensure high speed comparison and low power.This paper introduces the circuit design, simulation, tape out and final test results. The Spectre simulation results show that, the ADC has SNR of 68.4 dB and the SFDR is 76 dB. The chip area is 3.49×1.79 mm×mm. The test results show that the chip has SNR of 48.48 dB and the SFDR is 58.67 dB. The DNL is 12 LSB and the INL is 59 LSB. The chip has correction function.The gain non-linearity of OTA contributes most for the non-linearity of ADC. A digital calibration algorithm is studied in this paper, the behavioral simulation is done by matlab, and the evaluation results are showed.