A Optimization Design Of Pipeline ADC For DSP

A 12 bits pipeline-ADC with 16 channels of iuput,an autosequencer state machine for expanding ADC's application function and an interface circuit between ADC's analog and digital part was designed,they all were embedded in a 32 bits floating-point Digital Signal Processor(DSP).The circuit was simulated and fabricated based on GSMC 0.18 ?m CMOS process.Design focuses on the dc offset problem that commonly exists in the ADC,optimized the design of S/H circuit,at last,the problem of ADC's bottom waveform have all lost(equivalent to a DC offset)been solved successfully;For the front-end S/H circuit consumes a large amount of chip area,after the modification of increasing two reference voltage 1V and 2V in the op-amp,greatly reduced the area and increased the SLEW RATE(SR)compared with the traditional S/H circuit of charge transfer-structure;Considering the power consumption problem of the comparators,dynamic adjusting the switch of the secondary op-amp's DC path under the drive of the two-phase non-overlapping clock,in the sampling phase to keep the switch closed to complete the normal function of the comparator,while the phase of holding will keep open for energy conservation;Designed a MDAC circuit with a small number of combinational logic circuits and MOS switch,and an op amp,inplemented a function with both DAC and 8 times magnification,as well as residual function;According to the operation of the ADC in different frequency ? conversion time and sampling pulse widths,an autosequencer state machine is designed to implement serial(or sequenctial)/simultaneous sampling function of the ADC and to store the digital result in the corresponding RESULT register;Designed an interface circuit from analog module to digital module takes into account the ADC in different operating modes with different operating frequency and conversion time,so that ADC can cut off the path between the input terminals of the RESULT register and the output terminals of the 12-bit conversion result from the analog module at the right moment,the right conversion result,and then the correct conversion result is locked to the RESULT register.The simulation results of the ADC when a sine wave input VPP(Voltage Peak-Peak)is 3V and frequency is 100 KHz(1024 points at the fastest 12.5 MSPS sampling rate): the ENOB of 11.544 bits,SNDR of 71.26 dB,SNR of 72.36 dB,SFDR of 80.9 dB,THD of 77.21 dB,the total power consumption of about 112.2 mW,an area of about 800 ?m × 1200 ?m.The actual test results of the chip indicate that the DC offset value of the ADC is less than 1 LSB(plus the ADC offset calibration function).