The Research Of 10 Bit 20MSPS Pipelined A/D Converter

This paper describes a 10b, 20MSample/s pipelined A/D converter. It is one block of high performance and favorable dynamic-range CMOS Image Sensor. By analyzing the characters of several kinds of ADC and taking the requirement of CMOS Image Sensor into account, we select pipelined ADC to perform Analog-Digital Conversion of the analog signal which is sampled by the pixel. It can achieve high speed and resolution. Two main functions of ADC, sample and quantization by SC (switch capacitor) circuit are emphasized. Moreover, trade-offs of noise, speed and power in SC circuit and the principle of choosing sample capacitor are studied. And on the base of above researches, the frame and the circuit of the pipelined ADC is built. At last, operation principals of all modules in the ADC are analyzed, and simulation results are presented.The circuit is based on CMOS technology. Unlike a general sub-ranging converter, each block of pipelined ADC includes a sample and hold circuit to hold the analog input signal or residue signal. Therefore, in a pipelined analog to digital converter, a higher throughput rate can be obtained because a new sample can be taken as soon as the first stage of the pipeline has finished processing the old sample. Each stage of the pipelined ADC includes a flash ADC performing a coarse quantization. The quantized signal is subtracted from the input signal and the residue is amplified through the inter-stage amplifier to be sampled by the subsequent stage, which can be finished by a MDAC (Multiplying DAC). The module is implemented by full-differential switch-capacitor circuit. MDAC has functions of digital-to-analog conversion, subtraction, residue amplification and sample/hold through charge redistribution between input capacitors and feedback capacitors, which simplifies the structure of the ADC. The digital outputs of all stages corresponding to the analog signal are sent to digital correction-logic and synchronized. Redundancy is introduced to make the sum of the individual stage resolutions greater than the total resolution. Then the redundancy is removed by a digital-correction algorithm, so that the effects of the offset which exist in the comparator and inter-stage amplifier are eliminated. To minimize power dissipation, a control signal, STBY, is used, which can decrease bias current of the MDAC and comparator in Stand-by mode to save power.