Design And Realization Of 12Bit 200MS/s Pipelined ADC

Digital communication technique and semiconductor technology have been growing rapidly all these years. As a sequence, analog-to-digital converters, as the bridge of analog and digital circuit, are required to have more and more excellent performance. Pipelined ADC is the major architecture because of its outstanding characteristic on the trade-off between speed, resolution, square and power dissipation.This work design a 12-bit, 200 MHz samples/s low power dissipation pipelined ADC using TSMC 0.18μm CMOS process.This paper briefly analyses the theory and architecture of pipelined ADC,then by using Matlab’s Simulink module to create a mathematical model description of the system,in order to confirm the feasibility and stability of the system.Besides,we have simulate and analysis the effects of the several major non-ideal factors on the pipelined ADC’s output spectrum. At last, based on TSMC 0.18μm 1P4 M CMOS process,we have designed and simulated the all circuit and layout of the pipelined ADC. The key blocks are as follows: input buffer circuit, sample and hold circuit, multiplying digital-to-analog converter, comparator circuit, clock generation circuit, bandgap reference circuits and digital correction circuit. The ADC core consists of five 2.5-bit stages and a final 2-bit flash sub-ADC. A digital correction circuit is used to eliminate errors between stages and achieve 12-bit accuracy. A improvement structure of follower is used as input buffer before the sample and hold circuit, which have a high linearity and lower power consumption; While a flip-around sample and hold circuit was designed to reduce the power consumption; In sample and hold circuit and Multiplying DAC, a gain-boosting op amp was used to insure the speed and precision of the switch-capacitor circuit; In order to reduce the non-linear caused by the on-resistance of sample switch, a bootstrapped switch has been used in sample and hold circuit, first and second stage; Besides, a latch comparator with pre-amp has been used to realize fast compare and reduce the kick-back effect, which are full use of the amplifier negative exponential response and the dynamic latch positive exponential response advantages; The whole pipeline stage capacitances are scaled down, effectively reducing the power consumption of the circuit.The test results showed that the ADC achieves the spurious-free dynamic range(SFDR) of 83.39 dB, the signal-to-noise(SNR) of 60.00 dB and the effective bits of 9.68 bit for a sine signal with 0.625 V amplitude and 10 MHz frequency input at sampling rate of 200MHz;when the input frequency up to 70 MHz, the SFDR, SNR and ENOB are 74.93 dB,58.92 dB,9.47 Bit, which achieve high-speed and highresolution performance.