Research And Design Of 8-bit High-Speed Analog To Digital Converter

Analog-to-digital converters are the link between the analog world and the digital world.Especially now,digital systems and analog systems have covered all aspects of life.In the fields of high-speed mobile communications,wireless networks,and military radars,the requirements for data transmission and processing speeds are getting faster and faster,making the requirements for the higher speed of analog-to-digital converters in the system.The pipelined folding-interpolating A/D converters inherited the high speed advantage and broke through the resolution barrier of the flash A/D converter,which became hotspot of high-speed medium-resolution A/D converters in recent years.Firstly,this thesis introduced the basic principles of the folding-interpolating A/D converters A/D converter and the frequently-used architectures.On the basis of understanding its basic principle,a single-channel 1GS/s 8 bit F&I A/D converters is designed.And then study the key factors that affect the speed of it.In order to achieve the sample rate of 1GS/s,the architecture of the system is considered.A topology of parallel and cascaded folding is designed to restrain the frequency-multiplier effect;In this pipelined folding-interpolating architecture the parallel coarse channel has been eliminated,which inserts an additional interstage sample-and-hold circuit becoming the distributed sample-and-hold circuit between the cascaded folding stage and thus enable every stage circuit to process the signal parallelly;Five stages pipelined folding-interpolating architecture are designed in order to achieve 8 bit resolution.According to the structure parameters of the folding-interpolating A/D converter,we build a model,using Matlab&Simulink.The model proves the feasibility of theoretical analysis from functional aspect and guides the design of actual circuit.Secondly,it is considered on the circuit level.The bandwidth factor of folder be what we must first take into consideration,using the minimum folding coefficient;The structure of the traditional folder has been improved to increase the bandwidth of it;A high-speed preamplifier latch comparator is adopted to reduce conversion time;The distributed high speed comparators are designed to reduce the number of comparators.A single-channel sampling rate of 1GS/s 8-bit folding interpolation A/D converter was achieved based on 0.18?m CMOS process finally.Simulation results show that the circuit's SFDR is 62.44 dB,THD is-65.58 dB,ENOB is 7.94 bits with a 13.67 MHz sine wave input,a peak-to-peak value of 800 mV,2.0 voltage supply and 1 GS/s sample rate;When the frequency of input signal is 486.32 MHz and the other conditions is same,the simulation results show that the circuit's SFDR is 59.7 dB,THD is-66.7 dB,ENOB is 7.46 bits.