Design And Realization Of High-Resolution Folding And Interpolating Analog-to-Digital Converter

The research and development of analog-to-digital converters (ADCs) with highspeed, high precision and low power consumption are very significant in the design ofSOC applied in DSP such as wireless communication system and high-definition digitalvideo display. Based on nonlinear analog signal preprocessing, the folding techniquegreatly reduces the number of comparators and keeps such high speed as flash structure,but its resolution is limited to usually6-8bits due to process mismatch and nonlinearity.The folding and interpolating ADC with high resolution become a hot research in recentyears.Based on the transfer characteristics of the folding and interpolating circuits, abehavioral model of a10-bit folding and interpolating ADC is built in MATLAB.Performance degradation due to the nonideal effects such as limited bandwidth, gainmismatch, interpolation gain error and comparator offset are simulated and analyzed.Two two-stage-conversion architectures are designed for10-bit object. Consideringresolution limitation of folding and interpolation, a three-stage-conversion architecturewith pipelined folding is realized by the combination of folding and subranging. Themain contributions of precision optimization are followed:A high-performance sample-and-hold circuit is designed by unity-gain-samplestructure, a gain-enhance folded-cascode operational amplifier and rail-to-rail input toimprove the common-mode input range at low supply.A combined topology of parallel and cascaded folding is designed to reducenonlinearity and restrain the frequency-multiplier effect. Distributed interstagetrack/hold circuits realize the pipeline folding, relieve the settling requirement of eachstage, and make suitable folded signals without dc level shifting at high frequency.A offset-cancellation preamplifier eliminates the input offset voltage. Its kickbacknoise is alleviated effectually by neutralization technique. Its control logic is compatiblewith distributed interstage track/holds for pipelined folding.A cascaded resistive averaging interpolation is proposed to disperse highinterpolating rate to every stage for converting and folding. The linearity is improved,and the interpolating error of high rate is avoided. The boundary effect is eliminated byMoebius-band averaging network.A subraging-selected-crossing interpolation is designed. It extend the interpolatingrange, minimize interpolating error and use interpolating network more effectually for saving area and power.A bit-synchronized correction is implemented by odd-even parity algorithm. Thecorrected three-stage converted results output to avoid the error for multi-stageconversion.Based on above designs, a10-bit100-MS/s folding and interpolating ADC isrealized in SMIC0.18μm1P6M CMOS. The measured result is: the peak INL and DNLare±0.48LSB and±0.33LSB, respectively. The dissipation power is only95mW at1.8V power supply. Input range is1.0VP-Pwith2.29mm~2active area. At20MHzinput@100MS/s,9.59ENOB,59.5dB of SNDR and82.49dB of SFDR are achieved.A superior FOM of1.23pJ/Conv is acquired, which is the advanced level in thisdirection.