Research Of UHF RFID Frequency Synthesizer

With the development of wireless communication technology,frequency synthesizer has become one of the most critical elements in radar,navigation,wireless data communications,remote sensing,internet of things and other areas.The performance of frequency synthesizer has become the determinant factor of the whole communication system.Therefore,dedicated to the study and development of frequency synthesizer is an important research topic in the field of wireless communications in the world.Based on in-depth study of the PLL frequency synthesizer theoretical system,two key modules of VCO(Voltage Controlled Oscillator)and Prescaler(Frequency Divider)is improved,and a new UHF PLL frequency synthesizer circuit structure is proposed.The main work and innovations of this paper is as follows:(1)The overall structure of UHF frequency synthesizer is discussed.And the performance of PLL frequency synthesizer is analyzed and summarized.(2)A novel dual-modulus prescaler circuit is proposed.In this proposed circuit,the extended true single-phase clock technology(E-TSPC)is used.The circuit structure is a combination of two D flip-flops and two gates.It has the advantages of high frequency,low power consumption,small chip area and fast lock speed.(3)A new low phase noise quadrature voltage-controlled oscillator(LC-QVCO)circuit is proposed.It is based on the conventional LC-QVCO.By using switching technology and changing the signal connection,the new LC-QVCO has the advantages of low phase noise and low power consumption.(4)A novel structure of the UHF PLL frequency synthesizer is proposed.By using the new dual-modulus prescaler and LC-VCO,the design complexity of frequency divider and phase noise and the overall power consumption of the circuit has been reduced.The frequency synthesizer is implemented in Chartered 0.18-?m CMOS technology by Cadence and ADS simulation tools.Simulation results show that the maximum operating frequency of the proposed dual-modulus frequency divider can come up to 3.9GHz,the power consumption is 226 ?W,and the chip area is 0.067×0.046 mm2.The phase noise of the VCO is-124dBc/Hz at 1MHz offset.