Low Phase Noise Frequency Synthesizer For Single-chip CMOS UHF RFID Reader

With the rapidly development of RFID technology recently,it's necessary to provide high performance RFID read-write equipment.It's obviously that the ordinary RFID reader composed of discrete devices can't meet all the application market demands.And the single-chip CMOS UHF RFID reader draws more and more attention since its advantages of low manufacture-cost,low power-consumption,high performance and easy to be modular integrated.Especially promoted by the EPC ideas,products applied with RFID technology will soon be penetrated every aspect of people's daily life.There is no mature product of single-chip CMOS UHF RFID reader in market at present.This thesis focuses on the low phase noise frequency synthesizer applied in single-chip CMOS UHF RFID reader and implemented in RF CMOS technology.Characteristic works in the dissertation are summarized as follows:1) Based on the analysis of directly-conversed zero-intermediate frequency UHF RFID reader system,and according to EPC Global Class 1 Generation 2 protocol, design specifications are listed.Charge pump phase locked loop is choose to be the structure of frequency synthesizer and detail parameter of the PLL is calculated.2) Take noise performance as the prior consideration,the frequency synthesizer include VCO,Injection-Locked divider by 2,DSM,PFD,charge pump and LPF has been designed.3) The layout of frequency synthesizer is carried out and the BF-moat technology is applied to further suppress substrate noise feed-through effect.4) The whole frequency synthesizer is implemented based on IBM 0.18μm RF/MM CMOS process.Test results show that the phase noise of frequency synthesizer output signal achieved-125.26dBc/Hz@1MHz.