A Design Of Radio-Frequency Phase-locked Loop Frequency Synthesize Integrated Circuit Base On Wireless Communication

The frequency synthesizer is an important part in modern communication system. With the development of communication technique, the higher performance frequency synthesizer it required. Designing high performance frequency synthesizer is a very important research field in communication technique. The charge pump PLL (phase-locked loop) frequency synthesizer is widely used in communication system with its advantages such as high integration, low power consuming, no locked phase difference, low phase jitter.The basic operation principle of phase-locked frequency synthesizer composed of charge pump phase detector and passive loop filter is expatiated systematicly in this paper. The behavior of the phase noise, spur restraint and the locked time are analyzed in detail.A Design of Radio-Frequency phase-locked loop frequency synthesize Integrated Circuit based on wireless communication is given in this thesis. The prescaler and Voltage-controlled oscillator (VCO) is two difficult parts of the PLL. The SCL DFF is used and a Dual modulus Prescaler DFF structure is adopted in this design, which helps the prescaler to work at higher frequency. Fully integrated negative conductance Voltage Controlled Oscillator (VCO) is used in our design to achieve high frequency with low phase noise, and saves the chip area compared with LC oscillator. In the design of other building blocks of the PLL, TSPC DFF-based deadzone free PFD and the charge pump with tail current re-using are also adotped to improve the performance of the PLL.HJTC 0.35μm CMOS technology is used in this design, the power supply is 3.3V. The behavial-level and transistor-level simulation of the PLL shows that the overall performance of this PLL synthesizer can fulfill the requirements of wireless communication.Finally, the design work is summarized and the ideas and suggestions are presentated.