.2 ~ 2.4ghz Fractional-n Frequency Synthesizer Design,

RF receivers for.wireless communication applications require LO with low phase noise and small area. These requirements present challenges for frequency synthesizer design. The main purpose of this paper is to design a fractional-N frequency synthesizer for DTV-tuner applications and based on the purpose much detailed circuits analysis and design is carried out.Firstly, two different loop parameters design methods are compared. Loop phase noise characteristic are analyzed and MATLAB GUI is developed to get proper loop parameters. The MATLAB GUI significantly simplifies the loop parameter design process. For given loop parameters, complete simulation results can be obtained.Secondly, several key modules in frequency synthesizers are presented. Different non-ideal factors in charge pump design are considered and circuit tricks to suppress these factors are combined in the presented fully-differential charge pump. The synchronized 8/9 prescaler is adopted achieving the speed requirements without extra power consumption. In order to minimize the VCO phase noise degradation from power supply, a high PSR LDO is employed. The VCO is split into 64 sub-bands to obtain a small tune gain to ensure a small area of LPF and at the same time the loop phase noise can be optimized.Thirdly,the chip photograph and test results are presented which demonstrates the analysis method and circuits design. The implemented frequency synthesizer draws 10 mAfrom a 1.8 V supply while occupying about 1 mm2 die area in SMIC 0.18-μm CMOS process. The open loop bandwidth is 110 kHz and reference spur is less than-63 dBc. At 1 MHz frequency offset, the phase noise is less than-110 dBc/Hz. The RMS phase error integrated from 100 Hz to 100 MHz is less than 0.7°in integer-N mode and less than 1°in fractional-N mode.