Research On The Design Of Integrated Circuit Testability Based On Scan Design

Today, IP reuse technology has been widely used in the chip, through the chip reuse method, the size of the chip, power consumption, performance, and some other indicators have been relatively improved. But in the face of the complexity of the chips more and more, traditional testing methods can no longer meet the development speed of the chip, chip testing difficulty has caused the attention of relevant scholars,and for SoC test cost is the main factor-- Optimization of test time become the research direction of many scholars, by what means can better reduce the testing time,reduce test brought about by the high cost has become problems to be solved. By using testability technology, it can not only increase the controllability and observability of the chip circuit, but also reduce the testing difficulty of the chip.According to the design of the chip's testability, the biggest problem is the testing time. The main content of this paper:First of all, the research and design of the scan chain, the corresponding scan chain design optimization for different situations of the test vector unit, the main method of the re ranking algorithm and Huffman algorithm.Secondly, the test scheduling problem of multiple scan chain is discussed,including the BFD algorithm, MAV algorithm and TAD algorithm. And the corresponding scan chain design is compared to the three algorithms.Again, this paper also discusses the fault model test algorithm, under different fault conditions, the application of different test algorithms are compared.Finally, BIST module is set up testing, mainly from the test vector generator,read and write address generator and a feature value vector comparator of the correlation structure of RTL level design, and through Verdi fundamental training tool for simulation, to verify the correctness of the design.