Font Size: a A A

DFT Analysis And Optimization In PLC Chip

Posted on:2015-12-13Degree:MasterType:Thesis
Country:ChinaCandidate:J M QuFull Text:PDF
GTID:2298330452953254Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the feature size of digital IC shrinking to nanometer, the number of transistorsin one chip has reached to billion levels. As a result, in chip testing stage, the testpattern counts and test time has increased much, and the requirement on theperformance of test equipment is stricter. Test has been one of the most challengework in IC development.Because the test pattern count and test time increase sharply with the IC complexityrising in nanometer process. In order to reduce test time, we added test I/O intraditional method. However, test I/O count was limited for saving package cost.Therefore decreasing test time and test pattern count in project limited test I/O isbadly in need of solution saving test cost.The thesis offered a method, compress scan, aimed at decreasing test time and testpattern based on researching scan test theory and compressed circuit structure. Theidea of compress scan is reducing each scan chain length by increase scan chain countto reduce test time.The compress scan inserts test compress-circuit and uncompress-circuit in scanstructure. So that the scan chain count can be increased and not be limited by test I/Ocount. Then the test time decreases by a large margin. The thesis offers a new flow,compress scan flow, and optimizes the compress scan flow to reduce the extra areaadded by inserted circuit.The proposed approach completed DFT design for the power line communicationchip of Beijing Embeded System Key Lab successfully. It completed the DFT logicdesign, synthesis and scan insert. Compared to traditional scan, test time reduced37.3%and test pattern count reduced33%in nearly no area pay. The results show thatthe approach can reduce the test time and test pattern count effectively with no othercost.The significance of the paper is supplied a compress scan approach and offered anew scan flow. The flow applied successfully in real project. It reduced test time andtest pattern count in limited test I/O effectively. The research has very importantapplication value.
Keywords/Search Tags:Design for test, scan, test time, compress scan
PDF Full Text Request
Related items