Research On Test Time Optimization For 3D SoC

With the rapid development of integrated circuit technology and process,three dimensional integrated circuit has greatly increased the number of transistors by through-silicon via,and 3D integration is sure to become a cutting edge technology in semiconductor industry beyond Moore's Law.Compared with 2D SoC,3D SoC enjoys many obvious advantages,including higher integration,smaller chip size,higher test bandwidth,and lower test power.As the performance of 3D SoC enchances,its testing is confronted with greater challenges,including reduced observability,controllability,and rising testing costs.The core issue of optimizing 3D SoC is to control the test cost,and reduce test time.An approach to 3D SoC test optimization based on game theory is proposed to find a solution with optimal test time and test bandwidth.Under the constraints of the number of TSVs and the number of test pins,test time and test bandwidth interact and affect each other.The game try to find the Nash equilibrium solution between the two players.The values of equilibrium stimulus factor are set to randomly generate new decision combinations in the current equilibrium decision of the test time and test bandwidth,and then continue to play the game.Repeat the process of sequential optimization,and finally the global Pareto optimal solution is found,and the minimum test time is obtained.The experiments were performed on five different types of benchmark circuits.The experimental results show that the game theory used in this paper is better than the comparative algorithm in test time,and the method in this paper has obtained the optimal TAM structure design.A method for test time optimization for 3D SoC is presented.Reasonably distributing the elements so that the lengths of each scan chain are the approximately same and balanced,to get the minimum test time.The test time of a single IP core depends on the longest test wrapper scan chain in the IP core.In this case,the shorter the scan chain length,the less IP test time obtained.To reduce the total test time of 3D SoC,it is achieved by reducing the test time of a single IP core.Balanced the scan chains in the IP core is one of the most effective methods.The experiments wereperformed on five different types of benchmark circuits.The experimental results show that the proposed methed performs better than the greedy algorithm in test time.