New Approaches To Test Compression For Digital Circuits

Test compression has drawn significant attentions of academies and industries recently, since it can reduce test data volume and test application time of integrated circuits without losing fault coverage, therefore to diminish the gap between the test and manufacture camps. The test compression techniques can be classified to two categories, that is, test stimulus compression and test response compaction. This thesis conducts research on both fields and presents several compression methods. Two self-assembled complex circuits and industry circuits have been utilized to verify these compression methods. The contributions of the thesis include:1. This thesis presents a Variable-Tail code, and shows how to use this code to compress the test stimulus. Variable-Tail code like Golomb code is a variable-length-to-variable-length code, but it can achieve higher test compression ratio in the case of high X-bit density. To further reduce the test data volume and the test power dissipation, we also present an efficient Hamming-Distance reordering algorithm which improves the distribution of run-lengths. The experimental results show that the compression ratio of Variable-Tail with the proposed reordering algorithm is close to the theoretical upper bound of predictive codes(the average distance is only about 1.26% ) , and up to 20% of test power is saved.2. This thesis presents a parallel core wrapper design. The serial core wrapper designs bring the penalties of test application time and test power. Studying on the distributions of X-bit, we find the phenomenon of full overlapping and partial overlapping of scan slices. When the slices overlap continuously, they can be loaded only once, thus test application time and test power are significantly saved. The experimental results show when the parallel core wrapper design is applied, compared with the serial core wrapper design, the test application time is reduced to 2/3 and test power is reduced to 1/15.3. The 3X compression architecture is the main contribution of this thesis. The 3X architecture consists of three parts: X-Config stimulus compression, X-Balance test generation and X-Tolerant response compaction. X-Config stimulus decompression uses a...