Research On Optimization Techniques For SOC Test Time

There are many remarkable advantages of the SOC (System-on-a-Chip) which adopts the technique of reusable Intellectual-Property (IP) cores, such as high performance, small size, low power consumption, short development cycle, etc. The SOC has been widely used in various electronic devices and promots the performance of the Internet, information appliances, high-speed computing, multimedia technology and military electronic systems. However, the test time for SOC has increased dramatically because of the complexity of the chip and the diversity of IP cores. It has been the primary problem for SOC test to reduce the test time and lower the cost at the same time.Based on the composition of SOC, this dissertation proposes solutions to minimize and optimize test time from three levels, which are single IP core, SOC consisting of multiple IPs, hierarchical SOCs consisting of hierarchical IPs or SOC, respectively. It has been verified that the method put forward in the dissertation is valid and practical by the simulation experiments on the ITC '02 SOC test set.The main contents and research contributions of this dissertation are as follows.1. The scan chain balance is the only way to minimize IP core test time through the analysis of many IP core test methods. In order to overcome the shortcoming of existing scan chain partition methods, a novel method is proposed, which is called a scan chains balance algorithm base on twice-assigned method by the chains difference. And it also avoids the allocation problem caused by the great difference among scan chains within the IP cores. The scan chain consists of two parts, the standard and differential parts in this proposed method. The standard scan chains are allocated during the first distribution while differential scan chains are allocated with certain rules during the second, resulting in a more flexible scan chain distribution. It is proved that the time complexity of the proposed method is comparable with existing ones by theoretical analysis and the solutions are superior to existing ones by experimental results.2. The purpose of test scheduling is to reduce the test time by parallel test of IP cores in SOC at the premise of the minimum test time for each IP core. As the test scheduling problem has been verified to be NP problem, this dissertation adopts a new optimization algorithm based on probability density distribution called cross-entropy method for test scheduling. Experiments demonstrate that the method is of high efficiency when solving combinatorial optimization problem.3. A flexible TAM-bus assigned method is presented to divide the limitation of TAM continuous distribution in the internal IP cores assigned by the traditional test scheduling. This method takes full advantage of discontinuous spare TAM bus resources, ultimately resulting in minimizing SOC test time. Experimental results indicate that the presented method can achieve more optimized test time than traditional TAM allocation algorithms.4. Test time will be doubled if we apply the traditional SOC test architecture to hierarchical SOCs test because the traditional one lacks of the feature of hierarchy. Therefore, the dissertation introduces two improved structures for hierarchical SOCs test, which are bandwidth matching and transmission gate based parallel testing. The promoted structures lead to much shorter test time at the expense of a little hardware redundancy.5. Making full use of cross-entropy SOC test scheduling method and features of hierarchical SOCs test scheduling, this paper presents a time-divided IP core based test scheduling method. Test vectors are applied to the IP cores in groups and improved structures are designed for hierarchical SOCs test in the introduced algorithm, taking advantage of spare time during the test. The experimental results maintain that the time for hierarchical SOCs test has been further reduced by the proposed method.