Study And Design Of 12-bit Pipelined SAR ADC

Recent years, with the development of digital signal processing technology, the requirement of circuit system requires high speed, high precision and low power ADC in circuit system is increasing. The traditional Pipeline ADC is high speed, high precision, but high power consumption. While SAR ADC is low power consumption, but the speed and accuracy can only be limited to 100Ms/s and under 10-bit precision. In order to achieve a good balance in accuracy, speed, power consumption, Pipelined SAR ADC attract researchers’ attention. In this thesis, a 12-bit Pipelined SAR ADC with 20 MHz sampling rate is proposed with Global Foundry 180 nm CMOS technology.In order to achieve the high efficient of Pipelined SAR ADC, low power consumption structure, the self-temporal logic, reducing energy consumption, reducing the supply voltage, were used in the design.Firstly, low power consumption structure. The conventional RC SAR ADC structure was replaced by the full capacitance SAR ADC, which could reduce energy consumption and improve the speed of the system. To couple two sub grade SAR ADC, the traditional line of original MDAC cascade idea was replaced by the capacitance convert structure of successive approximation analog-to-digital converter which also simplified the circuit structure.Secondly, the design of the control logic timing. A shift register circuit was used in this design to control the working state of each module and the two sub grade ADC. According to two aspects of the design, one was the design of single stage sub grade ADC. The shift register and the control circuit was used to make the sub module circuit to meet the specific time specific module, which reduced the power consumption of single stage circuit. The other was the synchronization of the connection of the two sub grade ADC. Because of the complexity of the timing circuit of each single stage, a control module was designed to synchronous connection of the two stage, which accurately corresponded the front stage sub ADC of output amplifier working state to the after stage sub ADC of sampling state to ensure the normal work of the whole circuit.Thirdly, reducing amplifier power consumption. 1/4 amplification principle which uses 32 times circuit magnification to take the place of circuit of 128 times magnification was applied to decreases the output amplitude of amplifier, thus result in reducing amplifier power.Fourth, reducing the supply voltage. The power supply voltage of this design was changed from 1.8V to 1.2V, which effectively reduced the power consumption and therefore improved the efficiency of the ADC.Simulation results of the design show that the differential non-linearity(DNL) of the Pipelined SAR ADC is-0.3LSB~+0.3LSB, the integral non-linearity(INL) is-0.5LSB~+0.3LSB, the signal-to-noise-distortion ratio(SNDR) is 69.9064 d B, the effective-number-of-bits(ENOB) is 11.32, the power consumption is 132μW, and the figure-of-merit(FOM) is 30.5f J/c.-s, which means that the design has an ideal static and dynamic performance. The area of the core circuits is 1400μm×400μm. The final simulation results show that the ENOB of the ADC is 11.19, and FOM is 31.53 f J/c.-s., which demonstrate that the design of 12-bit Pipelined SAR ADC has initially achieved the goal.