A High-Speed Pipelined ADC Design For 5G Communication Base Station

The 4th generation mobile communication system(4G)has been popularized all over the world,and 5G R&D is the current research hotspot.Before the arrival of the 5G communication era,the design and layout of the base station needs to be updated.In the 5G base station,high-speed and high-precision ADC chips will be an indispensable part.The structures of high-speed ADCs mainly include flash,folding and interpolating,pipelined,successive approximation,etc.Compared to other structures,the pipelined ADC has the advantages of accuracy,speed,area and power consumption.With the upgrading of technology,the cut-off frequency of the device is up to 300 GHz in the advanced 40 nm CMOS process,where the intrinsic gain and output resistance of MOS are very poor.At low power supply voltage(1.2V),it is impossible to use a conventional high-gain operational amplifiers to implement high-speed,high-precision ADCs.After analyzing the working principle and error sources of traditional pipelined ADC,combining with SHA-less,gate voltage bootstrapping,capacitance scaling,swing scaling and bottom-plate sampling,this paper completed the following work:(1)In the first stage,switch-capacitor comparator is employed to handle the sampling networks mismatches betwen the input of the sub-ADC and the MDAC;(2)Pre-charging technique for threshold voltages relaxes the pressure of comparators in backend-ADC;(3)To resolve 3-bit in its first stage and amplify the residue by factor of 2 relax the requirement of opamp linearity and gain in the first MDAC;(4)Employing op-amp with high bandwidth and high linearity simplifies analog design and digital calibration;(5)The adjustable bias currents and feedback capacitances enhance the robustness of the ADC design;(6)Using custom single-ended output interfaces reduces output ports,saving the overall chip area.Afer the schematic was verified,based on 40 nm CMOS technology,the entire layout was arranged,and the drawing,post-simulation and optimization of the chip were independently completed.The overall chip area is 3mm?1mm.Referring to the simulation results at tt process and 55 degrees celsius,it achieves 11.2bit ENOB,70 dB SNR,82 dB SFDR with a 455 MHz,1.2V full-scale input after calibration,while consuming 185 mW if digital calibration block is not considered.