Design Of Pipelined Analog-to-Digital Converters And Study Of Digital Calibration Techniques

Modern RF communication systems are requiring for higher speed and higher resolution ADCs.However,high speed and high resolution circuit is not easy to achieve in deep submicron process.In recent years,considerable efforts have been spent on high-speed and high-resolution ADCs.A review of ADC structures and state-of-art ADCs was presented.Based on research,pipelined ADC is the most popular high-speed and high-resolution ADCs which are larger than 12-bit resolution and 50MS/s.This thesis presents the key technologies for pipelined ADCs.The linearity of the pipelined ADC is limited by capacitor mismatch,settling error and finite gain error.The non-linearity of the switches ON resistance reduces SFDR.The finite gain error can be reduced by high-gain OPAMP,and the settling error can be reduced by large slew rate and GBW.This thesis presents a Sample/Hold circuit which used in 14-bit ADCs.The S/H OPAMP has a gain of 116dB,GBW of 780MHz(4pF load capacitor),slew rate of 1100V/μs and 0.001%settling error of 5ns.Each pipeline stage was designed and optimized according to its specifications.A14-bit 100MS/s ADC was designed based on TSMC 0.18μm CMOS process model. Simulation results show that the ADC achieves 79dB SNDR,94dBc SFDR and-93dB THD. The total power dissipation is 750mW,and the analog part is 460mW.The die area of the chip is 5mm~2.Based on research of digital calibration techniques,a foreground digital calibration algorithm was simulated in behavioral level.In order to evaluate the effect of digital calibration, mismatches and thermal noise in pipeline stages were modeled.Simulation results show that,14-bit pipelined ADC with 0.1%capacitor mismatch has 71.3dB SNR before calibration and 76.8dB SNR after calibration.