.0.18 ¦¬m Cmos Pipelined Adc New Correction Algorithm

The development of digital communication and signal process system requires analog-to-digital converters (ADCs) with higher performance. The speed and resolutions of ADC almost have gone to utmost in the CMOS process if only rely on analog circuits design. Using calibration to compensate and correction errors is an important technique to improve the performance of ADCs. Calibration is a significant way to break the limitation of CMOS process in the current integrated circuits design technology.The pipelined multistage ADC architecture has become suitable for many applications because it can be insensitive to offsets in comparators and operational amplifiers by using redundancy and digital correction, and because it has advantages of high speed, high resolution, low power dissipations and consuming small chip area. In the traditional designs of pipelined ADCs, errors in the outputs can be sensed and corrected as long as the inter-stage gain is enough accurate. However, a key limitation of this technique is that such analog components are becoming more difficult to design in scaled technologies because of the reduced power-supply voltages.To overcome this problem, based on Redundant Signed Digit (RSD) structure of pipelined ADC, the thesis presents a background calibration technique to compensate the inters-stage gain error in pipelined ADCs. This compensation scheme can reduce the performance demands on high gain operational amplifiers and capacitor matching. And it can improve the system's linearity.Firstly, the thesis analyses the structure and conversion operations of the pipelined ADC with redundancy, especially the structure of multiplying digital-to- analog converters (MDAC). What should be focused on is the producing source of the inter-stage gain errors. On the basis of studying some inter-stage gain calibration technique for pipelined ADCs, the digital background calibration algorithm and structure is used in this thesis. A calibration signal is injected into stage input signal and processed simultaneously, which is controlled by pseudo random code. For sake of calibration signal, the inter-stage gain error can be measured, through which the calibration coefficient is adjusted actively, and then the gain errors will be corrected at digital domain background. And data conversion won't be interrupted because of background calibration technique. Secondly, the model of a 12-bit 100-MSample/s pipelined ADC is established which bases on the designed inter-stage gain error calibration algorithm. The MATLAB simulation results show that system linearity is improved by the calibration.Based on a 0.18μm SMIC Si-CMOS process, the digital background calibration circuit for the 12-bit 100-MSample/s pipelined ADC is simulated using HSPICE. The simulation results show that calibration circuits implement desired arithmetic, and inter-stage gain error has been better compensated. The circuits consume total power dissipation of 1.8mW at 1.8V supply voltage.