Design And Implementation Of Low Power Fractional N Frequency Synthesizer Based On Sub-GHz Wireless Communication Technology

The flourishing of ubiquitous wireless communication networks has promoted the development of complex RF systems.Concurrently,Wireless products have been integral part of our lives.A lot of wireless terminals and a variety of applications have scattered around us,such as smart home,automatic meter reading,lighting system,wireless body are network,industrial system,healthcare monitoring,bio-sensing,security systems,environmental applications,etc.Sub-GHz wireless technology is widely applied in above mentioned wireless and application systems.The frequency synthesizer is a key block in the wireless transceivers.The main research work of this thesis is to design a low-power and area-saving frequency synthesizer(FS)based on GSMC 130nm RF CMOS process,which can be used for Sub-GHz wireless transceiver system.Research achievement will be described in detail as follows.The principle and various type of phase-locked loop(PLL)are presented in the second chapter.Various typies of PLL and their system structure are reviewed.In terms of charge-pump PLL frequency synthesizer(CPPLL-FS),all of the important modules in system are analyzed both in the system and circuits perspective,including the phase frequency detector(PFD),charge pump(CP),loop filter(LF),voltage-controlled oscillator(VCO),divider(DIV)and delta-sigma modulator(DSM).The design strategies and methodologies of each module are presented.Some research techniques and several new solutions are proposed in the third chapter.Two solutions are proposed to eliminate the dead zone and to improve the cycle slipping in the PFD.A new differential charge pump with crossing over switch is proposed to reduce the common-mode noise.Several phase noise optimization techniques are introduced to improve the phase noise of voltage-controlled oscillator.A 4/4.5 divider with reduced quantization noise is reviewed and improved by a duty cycle calibration circuit,which is helpful for lower reference spurs.A new delta-sigma modulator with notch filter is proposed to reduce quantization noise in the special frequency synthesizer.Also,a new automatic frequency calibration algorithm based on the pulse swallow divider and its related circuits are introduced to accelerate the lock time of the loop.Based on the previous theoretical analysis and design strategy,an 900MHz-to-1.2GHz CPPLL-FS is implemented based on GSMC 130nm RF process,which is supplied by a 1.2V power supply and 10MHz?30MHz reference clock.The power dissipation is less than 5mW.All the design process is presented in fourth chapter,including circuit,layout,encapsulation and PCB.The measured results indicated that the chip works well in the Sub-GHz band.However,several bugs are also found and analyzed in this chapter.