Research Of High Performance CMOS Frequency Synthesizer

The phase-locked loop(PLL)frequency synthesizer is widely used in the front-end of the RF wireless transceiver to provide local oscillator(LO)for up-conversion or down-conversion.The shrinking of CMOS technology and increasing intrinsic frequency provide a reliable process for frequency synthesizer.In the indicators of the frequency synthesizer,the phase noise of the LO limits the SNR and the minimum BER of the system.Wideband,low phase noise and high efficient frequency synthesizers have been attention.This thesis focuses on high-performance CMOS frequency synthesizer.The specific research work is as following.Firstly,after introducing the system architecture and indicators,the S-domain LTI model of the PLL is established to analyze the loop characteristics.The third-order and fourth-order PLLs are analyzed for the loop stability and dynamic performance.The noise transfer function of the PLL can guide the design of system and circuits.Secondly,Class-C VCOs is an improved structure of traditional cross-coupled VCOs.Class-C VCOs have lower phase noise than traditional cross-coupled VCOs.However,the high-frequency Class-C VCO has poor reliability,amplitude instability and poor tuning linearity.To meet the requirements of phase noise and loop stability of frequency synthesizer,a low-noise and wideband Class-C VCO is designed.The VCO consists of two control loops,bias stabilized circuit and amplitude-adjustment circuit(AAC).The VCO with double feedback loop generates time-varying bias current at startup,and adjusts the output swing according to the specific needs after stabilization.The VCO is implemented in TSMC CMOS 65nm1P9M.The power is 8.2mW with supply voltage 1.2V.The frequency tuning range is10.3~11.96GHz and the tuning gain approximates 110MHz/V,when the phase noise at offset1MHz is no more than-106dBc/Hz,.When the dual loops are turned on,the AAC detects the amplitude and determines that the VCO needs to be adjusted.The phase noise at offset100 kHz can be reduced from-73 to-80dBc/Hz,while the phase noise at offset 1MHz can be reduced from-102 to-106dBc/Hz.Finally,this thesis implements the fractional-N PLL frequency synthesizer with dual-loop VCO in TSMC CMOS 65nm 1P9M.Since phase noise and settling time of the frequency synthesizer are affected by non-ideal factors,proper margin and configurable regulation become inevitable.The loop filter,and charge pump,frequency and phase detector,automatic frequency correction circuits are programmable.The method not only allows to overcome the changes in the external environment,and flexibly adjusts the loop bandwidth and settling time.The method can effectively attenuate the non-ideal factors outside the PLL.The bandgap provides a stable,temperature-free,low-noise reference current for the charge pump.The high-speed divider includes a high-speed prescaler and a multi-mode divider that degenerate TSPC flip-flops and combinatorial logic to reduce propagation delay and increase operating frequency.The digital??modulator controls the multi-model divider.The output of the frequency synthesizer uses a buffer circuit to match the 50 ohm test probe.The power consumption of the frequency synthesizer is 18.2mW under the supply voltage of 1.2V,the core area of the chip is 1.5mm~2(including on-chips loop filter).The test results show that the output frequency range is 10.3~11.96GHz,when the phase noise of the carrier frequency at offset 1MHz is no more than-106dBc/Hz.The bandwidth is 180 kHz,the integral jitter is less than 1ps.The reference spurious and fractional spurious are not more than-69.3dBc with a-228dB figure of merit.The AAC of the VCO detects output amplitude and determines that the VCO needs to increase the amplitude,and the phase noise at offset 100kHz can reduce from-73 to-80dBc/Hz from a carrier frequency 11.96GHz,while the phase noise at offset 1MHz decreases from-103 to-106dBc/Hz.