A Study And Design Of Sigma-Delta Modulator In Fractional-N Synthesizer

The wireless communication technology is getting widely used in information exchange field in modern society, and its development is inseparable from the support of related technologies, so more and more attentions are paid to the research of the wireless IC design technology. The frequency synthesizer is widely used in wireless communication, and it can provide not only stable local oscillator frequencies for wireless receivers, but also the desired clock frequencies for digital electronic systems. The performance of the frequency synthesizer can affect the performance of the whole system, therefore, it is very important to design a high speed frequency synthesizer with low phase noise, low power consumption and high integration. There are many implementation structures of frequency synthesizer, and the most commonly used is the structure based on Phase-Locked Loop(PLL), which adds a frequency divider circuit to the feedback loop of PLL, and the output signal of different frequency is achieved by adjusting the division ratio. The division ratio can be fractional or integer. Integer frequency synthesizer has the advantage of simple structure, but its frequency resolution is low. Based on it fractional-N frequency synthesizer has been developed. The fractional-N divider can achieve any decimal frequency division ratio, which means that the frequency of the output signal can be any times of the reference frequency, so its frequency resolution is improved. However, a shortcoming of this structure is that the variable division ratio will lead to the change of VCO’s control voltage, which means that fractional spur is created in output spectrum. This paper introduces a Sigma-Delta modulator to the fractional-N frequency synthesizer in order to solve this problem.Firstly, this article analyzes the principle and realization structure of fractional-N frequency synthesizer, then it researches the principle and noise shaping function of Sigma-Delta modulator. The research of the equivalent model and simulation results of the first-order Sigma-Delta modulator show that its output sequence still has obvious periodicity and can’t fix the fractional spur perfectly. In contrast, simulation results shows that the output sequence of high order Sigma-Delta modulator is more randomized, so it has a better noise shaping effect than single order structure does. Based on all above, this paper adopts a multi-stage noise shaping structure to design a MASH1-1-1 modulator with operating frequency of 16 MHz and data width of 24 bits. Ithas the advantages of simple structure and good stability. Its model is built with Simulink tool to perform power density spectrum simulation, and the result proves it a remarkable noise shaping effect. The code is written in Verilog HDL, then it is synthesized by Design Compiler to obtain the gate-level netlist for automatic layout generation. Static timing analysis is made and the result shows that the gate-level netlist meets the timing requirement. Finally, the layout of the SDM is given out.