Applicable In The Research And Design Of Low-noise Frequency Synthesizer 802.11a/b/g Zero-if Radio Transceiver System

Frequency synthesizer is an important building block in wireless radio frequency (RF) transceiver systems. Frequency synthesizer can provide stable and program-mmable local oscillator (LO) signals to RF transceivers. The maximum carrier frequency is up to 5.825GHz for IEEE 802.11a/b/g multi-mode transceivers. In order to adapt zero-IF transceiver system applications, the maximum frequency of the frequency synthesizer (FS) must be over 10GHz, which brings many challenges to the frequency synthesizer design. This dissertation is based on the applications of the IEEE 802.11a/b/g multi-mode RF transceivers, and is aiming at a 9-12GHz and low phase noise sigma-delta (∑△) fractional-N FS.Firstly, this dissertation describes the non-ideal effect of FS on the performance of wireless RF transceiver systems. And the specifications of FS for 802.11a/b/g system application are derived.Secondly, this dissertation introduces the principle of operation and basic function blocks of the frequency synthesizer, then each building block closed loop noise transfer function. According to above analysis we summarize the FS system design and optimization mehods. Meanwhile the architecture of the FS for 802.11a/b/g system application are discussedThe fourth chapter describes the design method of the key building blocks, which includes:1) 9-12GHz low phase noise VCO study and design:a current model VCO with source degeneration technique is used to lower the current source transistor noise, in terms of the digital controlled capacitor array (DCCA) influencing over the VCO's quality factor, and the optimization methods of the DCCA is presented; 2) Low current mismatch and low current variation charge pump design:the charge pump's non-ideal effects influences over the frequency synthesizer's phase noise. In terms of the conflict between low current mismatch and low dynamic current mismatch existing in conventional charge pump, a current compensation techniques charge pump is discussed; 3)High sensitivity and ultra-band divide-by-2 circuits study and design:the factor of limiting the sensitivity of the divide-by-2 circuits is given here and then a frequency self-adaptive divider is proposed; 4)Low dropout voltage regulator design:in terms of the conflict between power and stability, a compensation method based on dynamic compensation techniques is proposed; 5) In terms of lower the quantization noise of the IA modulator (SDM). a 7.5/8 division ratio divider and a 3-rd order single loop SDM are adopt. Above work were verified by testing.A∑△fraction-N frequency designed for 802.11a/b/g multi-mode system applications was implemented in a 0.13μm RF CMOS process. The measurement results show that the locking frequency range is 8.75-11.26GHz and the in-band phase noise less than -84dBc/Hz with the integrated phase error less than 1.18°. The reference spur is below-60dBc. The chip area is 1.26X 1.44 mm2 (including PADs and ESD circuits) with the core chip area 0.36 mm2. The power consumption is 39.6mW.