The Research Of A Sigma-delta Fractional-N Frequency Synthesizer Applied To Short Range Wireless Transceiver

Short range wireless communication device occupies the unlicensed IndustryScience Medical (ISM) frequency bands. It has been widely applied in the field ofremote meter reading, wireless security, device management and monitoring.Frequency synthesizers is the key block in the short range wireless transceiver, Itsperformance determines the whole performance of the transceiver. Compared with theinteger frequency synthesizer, fractional-N frequency synthesizer overcoming thetradeoffs between loop bandwidth and channel spacing. However it has the problem offractional spurs which causes by the periodic changing division. Fortunately it can besolved by adopting Σ-Δ modulation technique. This paper researches the Σ-Δ.fractional-N frequency synthesizer and completes the circuit design.This article introduced the principle of frequency synthesizer and its relatedparameters simply, then investigated the fractional-N frequency synthesizer whichsuppresses fractional spurs by using Σ-Δ modulator. By analysed the differenceesbetween single loop higher-order Σ-Δ modulator and MASH1-1-1Σ-Δ modulator, A17-bit input and3-bit output, third-order single loop Σ-Δ modulator was designed. Itsinput dithered by a pseudorandom signal to suppress the limit cycle. At last the circuitwas achieved by VerilogHDL.The VCO adopted the structure of multi band LC-VCO, five digitally controlled,binary weighted capacitor arrays was used to achieve a frequency tuning range of1.602GHz-1.88GHz while keeping its frequency tuning sensitivity small. We also usedcurrent-limiting resistor arrays to replace the current sources in tradition designs. Theresistors can help to control the output swing precisely to optimize the tradeoffbetween phase noise and power consumption.We also completed the other blocks in PLL loop and made some improves. Twodifferent delay time can be controlled to Eliminate the dead zone of PFD; Thecomplementary switches were adopted to minimize clock feedthrough and chargeinjection of the switches, and the source currents were dynamic matching by otherthree branches. A228-272Multimode programmable frequency divider based on the dual mode prescaler which adopt phase-switching technique was designed. Otherwisewe designed the crystal oscillator to produce reference frequency, and finished thelayout design of some analog blocks.By simulation test, the circuit module functions normally, the performance hasreached the requirements needed by the system. We modelled the whole system byVerilog-A and simulated, the loop lock time was about935.9s from power on.